Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751476AbdIMRkk (ORCPT ); Wed, 13 Sep 2017 13:40:40 -0400 Received: from mail-io0-f194.google.com ([209.85.223.194]:36075 "EHLO mail-io0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751365AbdIMRkf (ORCPT ); Wed, 13 Sep 2017 13:40:35 -0400 X-Google-Smtp-Source: AOwi7QBVITcthrdIvO0cx2PqEGskHXTa5pNTegiEZ/jBaUKYXOQchyzNkZu7WgDbM0zgbR3wpQGKcg== Date: Wed, 13 Sep 2017 12:40:32 -0500 From: Rob Herring To: Tirupathi Reddy Cc: sboyd@codeaurora.org, mturquette@baylibre.com, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Subject: Re: [PATCH V3] clk: qcom: Add spmi_pmic clock divider support Message-ID: <20170913174032.u33zzo64ipk22vgp@rob-hp-laptop> References: <1504699207-9568-1-git-send-email-tirupath@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1504699207-9568-1-git-send-email-tirupath@codeaurora.org> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2381 Lines: 81 On Wed, Sep 06, 2017 at 05:30:07PM +0530, Tirupathi Reddy wrote: > Clkdiv module provides a clock output on the PMIC with CXO as > the source. This clock can be routed through PMIC GPIOs. Add > a device driver to configure this clkdiv module. > > Signed-off-by: Tirupathi Reddy > --- > .../bindings/clock/clk-spmi-pmic-div.txt | 51 +++ > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clk-spmi-pmic-div.c | 342 +++++++++++++++++++++ > 4 files changed, 403 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt > create mode 100644 drivers/clk/qcom/clk-spmi-pmic-div.c > > diff --git a/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt > new file mode 100644 > index 0000000..8b84b32 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/clk-spmi-pmic-div.txt > @@ -0,0 +1,51 @@ > +Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv) > + > +clkdiv configures the clock frequency of a set of outputs on the PMIC. > +These clocks are typically wired through alternate functions on > +gpio pins. > + > +======================= > +Properties > +======================= > + > +- compatible > + Usage: required > + Value type: > + Definition: must be one of: > + "qcom,spmi-clkdiv" If this is not a fallback, drop it. > + "qcom,pm8998-clkdiv" > + > +- reg > + Usage: required > + Value type: > + Definition: Addresses and sizes for the memory of this CLKDIV > + peripheral. > + > +- clocks: > + Usage: required > + Value type: > + Definition: reference to the xo clock. > + > +- clock-names: > + Usage: required > + Value type: > + Definition: must be "xo". Missing #clock-cells > + > +======= > +Example > +======= > + > +pm8998_clk_divs: qcom,clkdiv@5b00 { clock@5b00 > + compatible = "qcom,pm8998-clkdiv"; > + reg = <0x5b00>; > + #clock-cells = <1>; > + clocks = <&xo_board>; > + clock-names = "xo"; > + > + assigned-clocks = <&pm8998_clk_divs 1>, > + <&pm8998_clk_divs 2>, > + <&pm8998_clk_divs 3>; > + assigned-clock-rates = <9600000>, > + <9600000>, > + <9600000>; > +};