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Date: Thu, 2 Nov 2000 19:23:41 +0100 (MET)
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Reply-To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
To: Ulrich Drepper <drepper@cygnus.com>
cc: root@chaos.analogic.com, kernel@kvack.org,
        "Dr. David Gilbert" <dg@px.uk.com>, linux-kernel@vger.kernel.org
Subject: Re: Dual XEON - >>SLOW<< on SMP
In-Reply-To: <m3bsvy2qlb.fsf@otr.mynet.cygnus.com>
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Organization: Technical University of Gdansk
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On 2 Nov 2000, Ulrich Drepper wrote:

> I'm seeing this as well, but only with PIII Xeon systems, not PII
> Xeon.  Every single timer interrupt on any CPU is accompanied by a NMI
> and LOC increment on every CPU.
> 
>            CPU0       CPU1       
>   0:     146727     153389    IO-APIC-edge  timer

 This is the legacy 8254 timer source, used for the system time, i.e. 
gettimeofday() and friends. 

> NMI:     300035     300035 

 This is the NMI watchdog at work.  Every tick of the legacy timer all
CPUs receive an NMI unless overridden by the "nmi_watchdog" command line
argument. 

> LOC:     300028     300028 

 This is the internal local APIC timer used for scheduling.  Every CPU is
equipped with such a private timer.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

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