Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751488AbdINUmU (ORCPT ); Thu, 14 Sep 2017 16:42:20 -0400 Received: from mail.kernel.org ([198.145.29.99]:45434 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751330AbdINUmT (ORCPT ); Thu, 14 Sep 2017 16:42:19 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3F36A21BCE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=atull@kernel.org X-Google-Smtp-Source: ADKCNb5yK2ApoCMXk97t2e2C3vxqxBKFUkq9zVRrB5JGgzsbr6deWYGD3w7uimqq8gkYzwZy6YnJtJjmus0+XeuSuY8= MIME-Version: 1.0 In-Reply-To: References: <20170913204841.2730-1-atull@kernel.org> <20170913204841.2730-18-atull@kernel.org> From: Alan Tull Date: Thu, 14 Sep 2017 15:41:37 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 17/18] fpga: clean up fpga Kconfig To: matthew.gerlach@linux.intel.com Cc: Moritz Fischer , linux-kernel , linux-fpga@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1479 Lines: 49 On Thu, Sep 14, 2017 at 10:56 AM, wrote: Hi Matthew, > > Hi Alan, > > s/mixxed/mixed/ > OK, I'll fix that. Alan > On Wed, 13 Sep 2017, Alan Tull wrote: > >> The fpga menuconfig has gotten messy. The bridges and managers are >> mixxed together. >> >> * Separate the bridges and things dependent on CONFIG_FPGA_BRIDGE >> from the managers. >> * Group the managers by vendor in order that they were added >> to the kernel. >> >> The following is what the menuconfig ends up looking like more or less >> (platform dependencies are hiding some of these on any given >> platform). >> >> --- FPGA Configuration Framework >> <*> Altera SOCFPGA FPGA Manager >> <*> Altera SoCFPGA Arria10 >> <*> Altera Partial Reconfiguration IP Core >> <*> Platform support of Altera Partial Reconfiguration IP Core >> <*> Altera FPGA Passive Serial over SPI >> <*> Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager >> <*> Xilinx Zynq FPGA >> <*> Xilinx Configuration over Slave Serial (SPI) >> <*> Lattice iCE40 SPI >> <*> Technologic Systems TS-73xx SBC FPGA Manager >> <*> FPGA Bridge Framework >> <*> Altera SoCFPGA FPGA Bridges >> <*> Altera FPGA Freeze Bridge >> <*> Xilinx LogiCORE PR Decoupler >> <*> FPGA Region >> <*> FPGA Region Device Tree Overlay Support >> >> Signed-off-by: Alan Tull >> --- >> v4: Patch added to patchset in v4