Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754815AbdIRNSz (ORCPT ); Mon, 18 Sep 2017 09:18:55 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:18004 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754268AbdIRNSx (ORCPT ); Mon, 18 Sep 2017 09:18:53 -0400 From: Fabrice Gasnier To: , CC: , , , , , , Subject: [PATCH] ARM: dts: stm32: Add lptimer definitions to stm32h743 Date: Mon, 18 Sep 2017 15:16:55 +0200 Message-ID: <1505740615-24920-1-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG4NODE2.st.com (10.75.127.11) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-09-18_04:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2968 Lines: 133 Add lptimer definitions, depending on features they provide: - lptimer1 & 2 can act as PWM, trigger and encoder/counter - lptimer3 can act as PWM and trigger - lptimer4 & 5 can act as PWM Signed-off-by: Fabrice Gasnier --- arch/arm/boot/dts/stm32h743.dtsi | 103 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 58ec227..de54123 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -66,6 +66,32 @@ clocks = <&timer_clk>; }; + lptimer1: timer@0x40002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40002400 0x400>; + clocks = <&timer_clk>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + usart2: serial@40004400 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40004400 0x400>; @@ -172,6 +198,83 @@ }; }; + lptimer2: timer@0x58002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002400 0x400>; + clocks = <&timer_clk>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@0x58002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002800 0x400>; + clocks = <&timer_clk>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@0x58002c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002c00 0x400>; + clocks = <&timer_clk>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + }; + + lptimer5: timer@0x58003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58003000 0x400>; + clocks = <&timer_clk>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + status = "disabled"; + }; + }; + adc_3: adc@58026000 { compatible = "st,stm32h7-adc-core"; reg = <0x58026000 0x400>; -- 1.9.1