Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751606AbdISG1m (ORCPT ); Tue, 19 Sep 2017 02:27:42 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:4497 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751408AbdISG1h (ORCPT ); Tue, 19 Sep 2017 02:27:37 -0400 X-UUID: 8b6619cec3444244a30ebca56f0df5c6-20170919 From: Ryder Lee To: Matthias Brugger CC: , , , , Ryder Lee Subject: [PATCH v1 2/4] arm: dts: mt7623: update pio, usb and crypto nodes Date: Tue, 19 Sep 2017 14:27:22 +0800 Message-ID: <1964ba22750c5720cdc07ebb77a63d6f80e1579e.1505801355.git.ryder.lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4259 Lines: 147 This patch updates pio, usb and crypto nodes to make them be consistent with the binding documents. Signed-off-by: Ryder Lee --- arch/arm/boot/dts/mt7623.dtsi | 52 ++++++++++++++++++++++--------------------- 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 381843e..9ec3767 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -226,21 +226,6 @@ #reset-cells = <1>; }; - pio: pinctrl@10005000 { - compatible = "mediatek,mt7623-pinctrl", - "mediatek,mt2701-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - interrupts = , - ; - }; - syscfg_pctl_a: syscfg@10005000 { compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; @@ -274,6 +259,20 @@ clock-names = "system-clk", "rtc-clk"; }; + pio: pinctrl@1000b000 { + compatible = "mediatek,mt7623-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + interrupts = , + ; + }; + pwrap: pwrap@1000d000 { compatible = "mediatek,mt7623-pwrap", "mediatek,mt2701-pwrap"; @@ -680,7 +679,7 @@ interrupts = ; clocks = <&hifsys CLK_HIFSYS_USB0PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "free_ck"; + clock-names = "sys_ck", "ref_ck"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; status = "disabled"; @@ -690,8 +689,6 @@ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; reg = <0 0x1a1c4000 0 0x0700>; - clocks = <&clk26m>; - clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -699,12 +696,16 @@ u2port0: usb-phy@1a1c4800 { reg = <0 0x1a1c4800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; u3port0: usb-phy@1a1c4900 { reg = <0 0x1a1c4900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; @@ -719,7 +720,7 @@ interrupts = ; clocks = <&hifsys CLK_HIFSYS_USB1PHY>, <&topckgen CLK_TOP_ETHIF_SEL>; - clock-names = "sys_ck", "free_ck"; + clock-names = "sys_ck", "ref_ck"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; status = "disabled"; @@ -729,8 +730,6 @@ compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy"; reg = <0 0x1a244000 0 0x0700>; - clocks = <&clk26m>; - clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -738,12 +737,16 @@ u2port1: usb-phy@1a244800 { reg = <0 0x1a244800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; u3port1: usb-phy@1a244900 { reg = <0 0x1a244900 0 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; @@ -784,16 +787,15 @@ }; crypto: crypto@1b240000 { - compatible = "mediatek,mt7623-crypto"; + compatible = "mediatek,eip97-crypto"; reg = <0 0x1b240000 0 0x20000>; interrupts = , , , , ; - clocks = <&topckgen CLK_TOP_ETHIF_SEL>, - <ðsys CLK_ETHSYS_CRYPTO>; - clock-names = "ethif","cryp"; + clocks = <ðsys CLK_ETHSYS_CRYPTO>; + clock-names = "cryp"; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; status = "disabled"; }; -- 1.9.1