Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751590AbdIUCRR (ORCPT ); Wed, 20 Sep 2017 22:17:17 -0400 Received: from mail-db5eur01on0081.outbound.protection.outlook.com ([104.47.2.81]:15552 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751283AbdIUCRP (ORCPT ); Wed, 20 Sep 2017 22:17:15 -0400 From: "A.s. Dong" To: Viresh Kumar , Dong Aisheng CC: "linux-pm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "sboyd@codeaurora.org" , "vireshk@kernel.org" , "nm@ti.com" , "rjw@rjwysocki.net" , "shawnguo@kernel.org" , Anson Huang , Jacky Bai Subject: RE: [PATCH 1/7] PM / OPP: Add platform specific set_clk function Thread-Topic: [PATCH 1/7] PM / OPP: Add platform specific set_clk function Thread-Index: AQHTHCpTV2idKDY7JEOg3AnCHSLNIaK8/VYAgACHhYCAAOFtgIAAYEng Date: Thu, 21 Sep 2017 02:17:10 +0000 Message-ID: References: <1503504610-12880-1-git-send-email-aisheng.dong@nxp.com> <1503504610-12880-2-git-send-email-aisheng.dong@nxp.com> <20170919225840.GI30848@ubuntu> <20170920070343.GA32187@b29396-OptiPlex-7040> <20170920203033.GD3001@ubuntu> In-Reply-To: <20170920203033.GD3001@ubuntu> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; 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x-ms-traffictypediagnostic: AM3PR04MB1345: x-exchange-antispam-report-test: UriScan:(31051911155226)(9452136761055)(258649278758335); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(5005006)(8121501046)(10201501046)(100000703101)(100105400095)(93006095)(93001095)(3002001)(6055026)(6041248)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123560025)(20161123558100)(20161123562025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);SRVR:AM3PR04MB1345;BCL:0;PCL:0;RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);SRVR:AM3PR04MB1345; x-forefront-prvs: 04371797A5 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Sep 2017 02:17:11.0889 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB1345 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v8L2Hpgj020031 Content-Length: 3679 Lines: 91 > -----Original Message----- > From: Viresh Kumar [mailto:viresh.kumar@linaro.org] > Sent: Thursday, September 21, 2017 4:31 AM > To: Dong Aisheng > Cc: A.s. Dong; linux-pm@vger.kernel.org; linux-kernel@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; sboyd@codeaurora.org; > vireshk@kernel.org; nm@ti.com; rjw@rjwysocki.net; shawnguo@kernel.org; > Anson Huang; Jacky Bai > Subject: Re: [PATCH 1/7] PM / OPP: Add platform specific set_clk function > > On 20-09-17, 15:03, Dong Aisheng wrote: > > I've been thinking of that before. > > Actually IMX already does some similar thing for MX5 (no for MX6). > > See: clk_cpu_set_rate() in drivers/clk/imx/clk-cpu.c. > > > > After some diggings, it seems MX7ULP is a bit more complicated than > > before mainly due to two reasons: > > 1) It requires to switch to different CPU mode accordingly when > > setting clocks rate. That means we need handle this in clock driver as > > well which looks not quite suitable although we could do if really want. > > > > 2) It uses different clocks for different CPU mode (RUN 416M or HSRUN > > 528M), and those clocks have some dependency. > > e.g. when setting HSRUN clock, we need change RUN clock parent to make > > sure the SPLL_PFD is got disabled before changing rate, as both CPU > > mode using the same parent SPLL_PFD clock. Doing this in clock driver > > also make things a bit more complicated. > > > > The whole follow would be something like below: > > static int imx7ulp_set_clk(struct device *dev, struct clk *clk, > > unsigned long old_freq, unsigned long > > new_freq) { > > u32 val; > > > > /* > > * Before changing the ARM core PLL, change the ARM clock soure > > * to FIRC first. > > */ > > if (new_freq >= HSRUN_FREQ) { > > clk_set_parent(clks[RUN_SCS_SEL].clk, clks[FIRC].clk); > > > > /* switch to HSRUN mode */ > > val = readl_relaxed(smc_base + SMC_PMCTRL); > > val |= (0x3 << 8); > > writel_relaxed(val, smc_base + SMC_PMCTRL); > > > > /* change the clock rate in HSRUN */ > > clk_set_rate(clks[SPLL_PFD0].clk, new_freq); > > clk_set_parent(clks[HSRUN_SCS_SEL].clk, > clks[SPLL_SEL].clk); > > } else { > > /* change the HSRUN clock to firc */ > > clk_set_parent(clks[HSRUN_SCS_SEL].clk, > > clks[FIRC].clk); > > > > /* switch to RUN mode */ > > val = readl_relaxed(smc_base + SMC_PMCTRL); > > val &= ~(0x3 << 8); > > writel_relaxed(val, smc_base + SMC_PMCTRL); > > > > clk_set_rate(clks[SPLL_PFD0].clk, new_freq); > > clk_set_parent(clks[RUN_SCS_SEL].clk, > clks[SPLL_SEL].clk); > > } > > > > return 0; > > } > > Right and we have the same thing in the cpufreq driver now. It will stay > at some place and we need to find the best one, keeping in mind that we > may or may not want to solve this problem in a generic way. > > > That's why i thought if we can make OPP core provide a way to handle > > such complicated things in platform specific cpufreq driver. > > > > How would you suggest for this issue? > > I wouldn't add an API into the OPP framework if I were you. There is just > too much code to add to the core to handle such platform specific stuff, > which you are anyway going to keep somewhere as it is. IMHO, keeping that > in the clock driver is a better thing to do than this. > Okay, I will give a try in CLK driver. Thanks for the suggestion. Regards Dong Aisheng > -- > viresh