Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751739AbdIULtm (ORCPT ); Thu, 21 Sep 2017 07:49:42 -0400 Received: from mail-io0-f194.google.com ([209.85.223.194]:38631 "EHLO mail-io0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751598AbdIULtl (ORCPT ); Thu, 21 Sep 2017 07:49:41 -0400 X-Google-Smtp-Source: AOwi7QD/otZJ+GsWC4LeIVOoN7WAif4KO8aSJXQOYU+yeLRHI6S/o5lX8CfZcNFpSvUFoK2LK7C+YYyqUPQkmW0cjrE= MIME-Version: 1.0 In-Reply-To: <1505973174-27961-1-git-send-email-jananis37@gmail.com> References: <1505973174-27961-1-git-send-email-jananis37@gmail.com> From: Martyn Welch Date: Thu, 21 Sep 2017 12:49:40 +0100 X-Google-Sender-Auth: fUSwXulUB4KsI4x-LjhAB2BwdBU Message-ID: Subject: Re: [PATCH] staging:vme Fix use BIT macro To: Janani Sankara Babu Cc: Greg KH , Manohar Vanga , antonl1911@gmail.com, Ricardo Silva , devel , LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1737 Lines: 43 On 21 September 2017 at 06:52, Janani Sankara Babu wrote: > This patch is created to solve the following warning shown by the checkpatch > script Warning: Replace all occurences of (1< > Signed-off-by: Janani Sankara Babu > --- > drivers/staging/vme/devices/vme_pio2.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/staging/vme/devices/vme_pio2.h b/drivers/staging/vme/devices/vme_pio2.h > index ac4a4ba..e9c3cf6 100644 > --- a/drivers/staging/vme/devices/vme_pio2.h > +++ b/drivers/staging/vme/devices/vme_pio2.h > @@ -179,7 +179,7 @@ > PIO2_REGS_CTRL_WRD1 }; > > #define PIO2_CNTR_SC_DEV0 0 > -#define PIO2_CNTR_SC_DEV1 (1 << 6) > +#define PIO2_CNTR_SC_DEV1 BIT(6) Sorry, these changes just don't make sense given the defines below. > #define PIO2_CNTR_SC_DEV2 (2 << 6) > #define PIO2_CNTR_SC_RDBACK (3 << 6) > > @@ -188,12 +188,12 @@ > PIO2_CNTR_SC_DEV1, PIO2_CNTR_SC_DEV2 }; > > #define PIO2_CNTR_RW_LATCH 0 > -#define PIO2_CNTR_RW_LSB (1 << 4) > +#define PIO2_CNTR_RW_LSB BIT(4) > #define PIO2_CNTR_RW_MSB (2 << 4) > #define PIO2_CNTR_RW_BOTH (3 << 4) > > #define PIO2_CNTR_MODE0 0 > -#define PIO2_CNTR_MODE1 (1 << 1) > +#define PIO2_CNTR_MODE1 BIT(1) > #define PIO2_CNTR_MODE2 (2 << 1) > #define PIO2_CNTR_MODE3 (3 << 1) > #define PIO2_CNTR_MODE4 (4 << 1) > -- > 1.9.1 >