Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752005AbdIUQvE (ORCPT ); Thu, 21 Sep 2017 12:51:04 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:49812 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751894AbdIUQtx (ORCPT ); Thu, 21 Sep 2017 12:49:53 -0400 X-Google-Smtp-Source: AOwi7QAypNwlOOYlEjOs0ajb8tXIb9ZkYNxbcZlTSqM44NPoySFxbp9jq8FxQW0tBkX12A4ZD8YP8w== From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh+dt@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v9 6/7] dt-bindings: clock: Document qcom,apcs binding Date: Thu, 21 Sep 2017 19:49:39 +0300 Message-Id: <20170921164940.20343-7-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921164940.20343-1-georgi.djakov@linaro.org> References: <20170921164940.20343-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1411 Lines: 43 Add device-tree binding documentation for the Qualcom APCS clock controller. This clock controller is a mux and half-integer divider and provides the clock for the application CPU. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,apcs.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,apcs.txt diff --git a/Documentation/devicetree/bindings/clock/qcom,apcs.txt b/Documentation/devicetree/bindings/clock/qcom,apcs.txt new file mode 100644 index 000000000000..8083bcc33ebe --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,apcs.txt @@ -0,0 +1,27 @@ +Qualcomm APCS Clock Controller Binding +-------------------------------------- +The APCS hardware block provides a combined mux and half-integer divider +functionality. It is used for a main CPU clock mux on MSM8916 platforms. + +Required properties : +- compatible : shall contain only one of the following: + + "qcom,msm8916-apcs-clk" + +- clocks : shall be the phandle to the main input CPU PLL clock + +- #clock-cells : must be set to <0> + +Example: + + apcs: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global"; + reg = <0xb011000 0x1000>; + #mbox-cells = <1>; + + apcs_clk: apcs_clk { + compatible = "qcom,msm8916-apcs-clk"; + clocks = <&a53pll>; + #clock-cells = <0>; + }; + };