Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752072AbdIVJpW (ORCPT ); Fri, 22 Sep 2017 05:45:22 -0400 Received: from mail-io0-f170.google.com ([209.85.223.170]:50717 "EHLO mail-io0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752056AbdIVJpT (ORCPT ); Fri, 22 Sep 2017 05:45:19 -0400 X-Google-Smtp-Source: AOwi7QCcBQl/NJLgfo70rQlylj+0pW28AqxobsuxDjO5r7QzMUbAASNU2AZOjsnWNgHny8QrR6dQRCrOGikXPa29p90= MIME-Version: 1.0 In-Reply-To: <1504900113-8983-1-git-send-email-vdumpa@nvidia.com> References: <1504900113-8983-1-git-send-email-vdumpa@nvidia.com> From: Ulf Hansson Date: Fri, 22 Sep 2017 11:45:18 +0200 Message-ID: Subject: Re: [PATCH] mmc: tegra: Mark 64 bit dma broken on Tegra186 To: Krishna Reddy Cc: Adrian Hunter , Thierry Reding , Jon Hunter , "linux-mmc@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1653 Lines: 41 On 8 September 2017 at 21:48, Krishna Reddy wrote: > SDHCI controllers on Tegra186 support 40 bit addressing. > IOVA addresses are 48-bit wide on Tegra186. > SDHCI host common code sets dma mask as either 32-bit or 64-bit. > To avoid access issues when SMMU is enabled, disable 64-bit dma. > > Signed-off-by: Krishna Reddy Thanks, applied for next! Kind regards Uffe > --- > drivers/mmc/host/sdhci-tegra.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c > index 0cd6fa80db66..b877c13184c2 100644 > --- a/drivers/mmc/host/sdhci-tegra.c > +++ b/drivers/mmc/host/sdhci-tegra.c > @@ -422,7 +422,15 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { > SDHCI_QUIRK_NO_HISPD_BIT | > SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | > SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, > - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > + /* SDHCI controllers on Tegra186 support 40-bit addressing. > + * IOVA addresses are 48-bit wide on Tegra186. > + * With 64-bit dma mask used for SDHCI, accesses can > + * be broken. Disable 64-bit dma, which would fall back > + * to 32-bit dma mask. Ideally 40-bit dma mask would work, > + * But it is not supported as of now. > + */ > + SDHCI_QUIRK2_BROKEN_64_BIT_DMA, > .ops = &tegra114_sdhci_ops, > }; > > -- > 2.1.4 >