Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933630AbdIXUqI (ORCPT ); Sun, 24 Sep 2017 16:46:08 -0400 Received: from mail.linuxfoundation.org ([140.211.169.12]:33016 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933137AbdIXUoc (ORCPT ); Sun, 24 Sep 2017 16:44:32 -0400 From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Anup Patel , Ray Jui , Scott Branden , Jassi Brar Subject: [PATCH 4.13 073/109] mailbox: bcm-flexrm-mailbox: Fix mask used in CMPL_START_ADDR_VALUE() Date: Sun, 24 Sep 2017 22:33:34 +0200 Message-Id: <20170924203356.030056553@linuxfoundation.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170924203353.104695385@linuxfoundation.org> References: <20170924203353.104695385@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1270 Lines: 39 4.13-stable review patch. If anyone has any objections, please let me know. ------------------ From: Anup Patel commit 6d2061b981af165d3e45462e0804b5a1f2f4c7bc upstream. The mask used in CMPL_START_ADDR_VALUE() should be 27bits instead of 26bits. This incorrect mask was causing completion writes to 40bits physical address fail. This patch fixes mask used in CMPL_START_ADDR_VALUE() macro. Fixes: dbc049eee730 ("mailbox: Add driver for Broadcom FlexRM ring manager") Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Jassi Brar Signed-off-by: Greg Kroah-Hartman --- drivers/mailbox/bcm-flexrm-mailbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/mailbox/bcm-flexrm-mailbox.c +++ b/drivers/mailbox/bcm-flexrm-mailbox.c @@ -95,7 +95,7 @@ /* Register RING_CMPL_START_ADDR fields */ #define CMPL_START_ADDR_VALUE(pa) \ - ((u32)((((u64)(pa)) >> RING_CMPL_ALIGN_ORDER) & 0x03ffffff)) + ((u32)((((u64)(pa)) >> RING_CMPL_ALIGN_ORDER) & 0x07ffffff)) /* Register RING_CONTROL fields */ #define CONTROL_MASK_DISABLE_CONTROL 12