Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933281AbdIYAEc (ORCPT ); Sun, 24 Sep 2017 20:04:32 -0400 Received: from mail-out-2.itc.rwth-aachen.de ([134.130.5.47]:52327 "EHLO mail-out-2.itc.rwth-aachen.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932844AbdIYADH (ORCPT ); Sun, 24 Sep 2017 20:03:07 -0400 X-IronPort-AV: E=Sophos;i="5.42,434,1500933600"; d="scan'208";a="14891869" From: =?UTF-8?q?Stefan=20Br=C3=BCns?= To: CC: , Chen-Yu Tsai , Andre Przywara , , Dan Williams , Vinod Koul , Rob Herring , , Code Kipper , Maxime Ripard , , =?UTF-8?q?Stefan=20Br=C3=BCns?= Subject: [PATCH v3 08/10] dmaengine: sun6i: Add support for Allwinner A64 and compatibles Date: Mon, 25 Sep 2017 02:02:42 +0200 X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170925000244.11679-1-stefan.bruens@rwth-aachen.de> References: <20170925000244.11679-1-stefan.bruens@rwth-aachen.de> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [77.182.212.37] X-ClientProxiedBy: rwthex-s3-b.rwth-ad.de (2002:8682:1aa1::8682:1aa1) To rwthex-w2-a.rwth-ad.de (2002:8682:1a9e::8682:1a9e) Message-ID: <6c3aee4d-3a08-4d41-9e31-f1fb817a691f@rwthex-w2-a.rwth-ad.de> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2167 Lines: 58 The A64 SoC has the same dma engine as the H3 (sun8i), with a reduced amount of physical channels. To allow future reuse of the compatible, leave the channel count etc. in the config data blank and retrieve it from the devicetree. Signed-off-by: Stefan Brüns Acked-by: Maxime Ripard --- Changes in v3: - Omit default values from sun50i_a64_dma_cfg definition Changes in v2: None drivers/dma/sun6i-dma.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 34d70af442ff..b4e759f4aa75 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -1122,6 +1122,25 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); }; +/* + * The A64 binding uses the number of dma channels from the + * device tree node. + */ +static struct sun6i_dma_config sun50i_a64_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3; + .set_burst_length = sun6i_set_burst_length_h3; + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16); + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16); + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); + .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); +}; + /* * The V3s have only 8 physical channels, a maximum DRQ port id of 23, * and a total of 24 usable source and destination endpoints. @@ -1149,6 +1168,7 @@ static const struct of_device_id sun6i_dma_match[] = { { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg }, { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg }, + { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sun6i_dma_match); -- 2.14.1