Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753901AbdIYKK1 (ORCPT ); Mon, 25 Sep 2017 06:10:27 -0400 Received: from terminus.zytor.com ([65.50.211.136]:54431 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932804AbdIYKKY (ORCPT ); Mon, 25 Sep 2017 06:10:24 -0400 Date: Mon, 25 Sep 2017 03:09:18 -0700 From: tip-bot for Kan Liang Message-ID: Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, tglx@linutronix.de, Kan.liang@intel.com, mingo@kernel.org Reply-To: linux-kernel@vger.kernel.org, hpa@zytor.com, tglx@linutronix.de, Kan.liang@intel.com, mingo@kernel.org In-Reply-To: <20170908213449.6224-2-kan.liang@intel.com> References: <20170908213449.6224-2-kan.liang@intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/urgent] perf/x86/msr: Add missing CPU IDs Git-Commit-ID: 1aaccc40a1864053da26605b0297be16dd52641e X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1325 Lines: 43 Commit-ID: 1aaccc40a1864053da26605b0297be16dd52641e Gitweb: http://git.kernel.org/tip/1aaccc40a1864053da26605b0297be16dd52641e Author: Kan Liang AuthorDate: Fri, 8 Sep 2017 17:34:48 -0400 Committer: Thomas Gleixner CommitDate: Mon, 25 Sep 2017 09:36:17 +0200 perf/x86/msr: Add missing CPU IDs Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well. Signed-off-by: Kan Liang Signed-off-by: Thomas Gleixner Cc: ak@linux.intel.com Cc: peterz@infradead.org Cc: piotr.luc@intel.com Cc: harry.pan@intel.com Cc: srinivas.pandruvada@linux.intel.com Link: http://lkml.kernel.org/r/20170908213449.6224-2-kan.liang@intel.com --- arch/x86/events/msr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 4bb3ec6..0672367 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -63,6 +63,14 @@ static bool test_intel(int idx) case INTEL_FAM6_ATOM_SILVERMONT1: case INTEL_FAM6_ATOM_SILVERMONT2: case INTEL_FAM6_ATOM_AIRMONT: + + case INTEL_FAM6_ATOM_GOLDMONT: + case INTEL_FAM6_ATOM_DENVERTON: + + case INTEL_FAM6_ATOM_GEMINI_LAKE: + + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: if (idx == PERF_MSR_SMI) return true; break;