Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934877AbdIYWlp (ORCPT ); Mon, 25 Sep 2017 18:41:45 -0400 Received: from mga05.intel.com ([192.55.52.43]:44663 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934254AbdIYWlo (ORCPT ); Mon, 25 Sep 2017 18:41:44 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,437,1500966000"; d="scan'208";a="153240557" Date: Mon, 25 Sep 2017 15:41:40 -0700 (PDT) From: matthew.gerlach@linux.intel.com X-X-Sender: mgerlach@mgerlach-VirtualBox To: Marek Vasut cc: Vignesh R , Cyrille Pitchen , David Woodhouse , Brian Norris , Boris Brezillon , Rob Herring , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel Subject: Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support In-Reply-To: Message-ID: References: <20170924105924.23923-1-vigneshr@ti.com> <20170924105924.23923-6-vigneshr@ti.com> <3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com> <4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com> <038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1688 Lines: 51 On Sun, 24 Sep 2017, Marek Vasut wrote: > On 09/24/2017 03:27 PM, Vignesh R wrote: >> >> >> On 9/24/2017 6:42 PM, Marek Vasut wrote: >>> On 09/24/2017 03:08 PM, Vignesh R wrote: >>>> >>>> >>>> On 9/24/2017 5:31 PM, Marek Vasut wrote: >>>>> On 09/24/2017 12:59 PM, Vignesh R wrote: >>>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to >>>>>> switch on QSPI power domain on TI 66AK2G SoC during probe. >>>>>> >>>>>> Signed-off-by: Vignesh R >>>>> >>>>> Are you planning to add some more fine-grained PM control later? >>>> >>>> Yes, I will need to add fine-grained PM control at some point. But, for >>>> now SoC does not really support low power mode or runtime power saving >>>> option. >>>> The fact that driver still uses clk_prepare_*() calls to enable/disable >>>> clocks instead of pm_*() calls makes it a bit tricky though. >>>> >>>> Just figured out I forgot to add cleanup code in error handling path of >>>> probe(). Will fix that and send a v4. >>> >>> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM >>> either, so it's fine for now. >>> >> >> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >> if its possible to get rid of clk_*() calls in favor of pm_*() calls. > > Not of the top of my head, sorry. +CC Matthew, he should know. I am not an expert at the clock framework nor the power management, but I did ask around a bit. No one I asked was planning to change the clk_*() calls to pm_*() call, but the feedback was that it would be a good idea. Matthew Gerlach > > -- > Best regards, > Marek Vasut >