Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966553AbdIYXtv (ORCPT ); Mon, 25 Sep 2017 19:49:51 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:35058 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965020AbdIYXtt (ORCPT ); Mon, 25 Sep 2017 19:49:49 -0400 X-Google-Smtp-Source: AOwi7QAY4K0fnwdEzCNtEbunxIUGo+3ct5X7Bc9e4QkYR5prflXQ00/qNtITRrTl7J3b1foRA1LOvg== Subject: Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support To: matthew.gerlach@linux.intel.com Cc: Vignesh R , Cyrille Pitchen , David Woodhouse , Brian Norris , Boris Brezillon , Rob Herring , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel References: <20170924105924.23923-1-vigneshr@ti.com> <20170924105924.23923-6-vigneshr@ti.com> <3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com> <4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com> <038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com> From: Marek Vasut Message-ID: Date: Tue, 26 Sep 2017 01:49:46 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1893 Lines: 53 On 09/26/2017 12:41 AM, matthew.gerlach@linux.intel.com wrote: > > > On Sun, 24 Sep 2017, Marek Vasut wrote: > >> On 09/24/2017 03:27 PM, Vignesh R wrote: >>> >>> >>> On 9/24/2017 6:42 PM, Marek Vasut wrote: >>>> On 09/24/2017 03:08 PM, Vignesh R wrote: >>>>> >>>>> >>>>> On 9/24/2017 5:31 PM, Marek Vasut wrote: >>>>>> On 09/24/2017 12:59 PM, Vignesh R wrote: >>>>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to >>>>>>> switch on QSPI power domain on TI 66AK2G SoC during probe. >>>>>>> >>>>>>> Signed-off-by: Vignesh R >>>>>> >>>>>> Are you planning to add some more fine-grained PM control later? >>>>> >>>>> Yes, I will need to add fine-grained PM control at some point. But, >>>>> for >>>>> now SoC does not really support low power mode or runtime power saving >>>>> option. >>>>> The fact that driver still uses clk_prepare_*() calls to >>>>> enable/disable >>>>> clocks instead of pm_*() calls makes it a bit tricky though. >>>>> >>>>> Just figured out I forgot to add cleanup code in error handling >>>>> path of >>>>> probe(). Will fix that and send a v4. >>>> >>>> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM >>>> either, so it's fine for now. >>>> >>> >>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >>> if its possible to get rid of clk_*() calls in favor of pm_*() calls. >> >> Not of the top of my head, sorry. +CC Matthew, he should know. > > I am not an expert at the clock framework nor the power management, but I > did ask around a bit.  No one I asked was planning to change the clk_*() > calls to pm_*() call, but the feedback was that it would be a good idea. The question is, if we do the replacement, will it break on socfpga ? A quick test might be useful. -- Best regards, Marek Vasut