Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936433AbdIZERJ (ORCPT ); Tue, 26 Sep 2017 00:17:09 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:47807 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935781AbdIZERF (ORCPT ); Tue, 26 Sep 2017 00:17:05 -0400 From: Kalyan Kinthada To: dwmw2@infradead.org, computersforpeace@gmail.com, boris.brezillon@free-electrons.com, marek.vasut@gmail.com, richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org, mark.rutland@arm.com, ezequiel.garcia@free-electrons.com, devicetree@vger.kernel.org Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, chris.packham@alliedtelesis.co.nz, Kalyan Kinthada Subject: [PATCH 1/2] dt-bindings: mtd: pxa3xx: Add "marvell,nand-force-csx" compatible string Date: Tue, 26 Sep 2017 17:16:59 +1300 Message-Id: <20170926041700.22663-2-kalyan.kinthada@alliedtelesis.co.nz> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926041700.22663-1-kalyan.kinthada@alliedtelesis.co.nz> References: <20170926041700.22663-1-kalyan.kinthada@alliedtelesis.co.nz> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1191 Lines: 27 When the arbitration between NOR and NAND flash is enabled the field bit[21] in the Data Flash Control Register needs to be set to 1 according to guidleine GL-5830741. This patch introduces a new compatible string "marvell,nand-force-csx" which is activated through device tree to implement the guideline GL-5830741. Signed-off-by: Kalyan Kinthada --- Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt index d9b655f11048..157ca7efa3d3 100644 --- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt +++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt @@ -20,6 +20,7 @@ Optional properties: not present false - nand-ecc-strength: number of bits to correct per ECC step - nand-ecc-step-size: number of data bytes covered by a single ECC step + - marvell,nand-force-csx: Set to implement guideline when arbitration of NAND and NOR flash is enabled. The following ECC strength and step size are currently supported: -- 2.14.1