Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967775AbdIZH4P (ORCPT ); Tue, 26 Sep 2017 03:56:15 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:35636 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965643AbdIZH4N (ORCPT ); Tue, 26 Sep 2017 03:56:13 -0400 X-Google-Smtp-Source: AOwi7QCe0oZHQGJS0h5tss0N3L+o9PW6/cdj6+DAgupH/2DkyWoZO9dLrTXTRsYorvm+oNM528qIQA== From: Nickey Yang To: mark.yao@rock-chips.com, robh+dt@kernel.org, heiko@sntech.de, mark.rutland@arm.com, airlied@linux.ie Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, seanpaul@chromium.org, briannorris@chromium.org, hl@rock-chips.com, zyw@rock-chips.com, bivvy.bi@rock-chips.com, xbl@rock-chips.com, nickey.yang@rock-chips.com Subject: [PATCH v2 6/8] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock Date: Tue, 26 Sep 2017 15:55:21 +0800 Message-Id: <1506412523-1766-6-git-send-email-nickey.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506412523-1766-1-git-send-email-nickey.yang@rock-chips.com> References: <1506412523-1766-1-git-send-email-nickey.yang@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 945 Lines: 24 Mipi-dphy's ref_clk connect to clk_dphy_pll inside rk3399. clk_24m -> Gate11[14] -> clk_mipidphy_ref -> Gate21[0] -> clk_dphy_pll So correct it. Signed-off-by: Nickey Yang --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3..6aa43fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1629,7 +1629,7 @@ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = ; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_DPHY_TX0_CFG>; clock-names = "ref", "pclk", "phy_cfg"; power-domains = <&power RK3399_PD_VIO>; -- 1.9.1