Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031045AbdIZOwM (ORCPT ); Tue, 26 Sep 2017 10:52:12 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4319 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967571AbdIZOwJ (ORCPT ); Tue, 26 Sep 2017 10:52:09 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Sep 2017 07:51:49 -0700 Subject: Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller To: Dmitry Osipenko , Thierry Reding , Laxman Dewangan , "Peter De Schrijver" , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , Vinod Koul CC: , , , , References: <604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com> From: Jon Hunter Message-ID: Date: Tue, 26 Sep 2017 15:50:03 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <604d92036e0936443290e68a2226f935fb348113.1506380746.git.digetx@gmail.com> X-Originating-IP: [10.21.132.144] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1412 Lines: 37 On 26/09/17 00:22, Dmitry Osipenko wrote: > Document DT bindings for NVIDIA Tegra AHB DMA controller that presents > on Tegra20/30 SoC's. > > Signed-off-by: Dmitry Osipenko > --- > .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt > > diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt > new file mode 100644 > index 000000000000..2af9aa76ae11 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt > @@ -0,0 +1,23 @@ > +* NVIDIA Tegra AHB DMA controller > + > +Required properties: > +- compatible: Must be "nvidia,tegra20-ahbdma" > +- reg: Should contain registers base address and length. > +- interrupts: Should contain one entry, DMA controller interrupt. > +- clocks: Should contain one entry, DMA controller clock. > +- resets : Should contain one entry, DMA controller reset. > +- #dma-cells: Should be <1>. The cell represents DMA request select value > + for the peripheral. For more details consult the Tegra TRM's > + documentation, in particular AHB DMA channel control register > + REQ_SEL field. What about the TRIG_SEL field? Do we need to handle this here as well? Cheers Jon -- nvpublic