Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032936AbdI0AzZ (ORCPT ); Tue, 26 Sep 2017 20:55:25 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:49744 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935998AbdI0AzV (ORCPT ); Tue, 26 Sep 2017 20:55:21 -0400 From: Kalyan Kinthada To: dwmw2@infradead.org, computersforpeace@gmail.com, boris.brezillon@free-electrons.com, marek.vasut@gmail.com, richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org, mark.rutland@arm.com, ezequiel.garcia@free-electrons.com, miquel.raynal@free-electrons.com, devicetree@vger.kernel.org Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, chris.packham@alliedtelesis.co.nz, Kalyan Kinthada Subject: [PATCH v2 0/1] Set FORCE_CSX bit when arbitration between NAND and NOR is enabled. Date: Wed, 27 Sep 2017 13:55:15 +1300 Message-Id: <20170927005516.28374-1-kalyan.kinthada@alliedtelesis.co.nz> X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 814 Lines: 26 When the arbitration between NOR and NAND flash is enabled the field bit[21] in the Data Flash Control Register needs to be set to 1 according to guidleine GL-5830741. Set the FORCE_CSX bit in NDCR for ARMADA370 variants as the arbitration is always enabled by default. Changes since v1: Thanks Miquel RAYNAL for the suggestion. * Deleted: "dt-bindings: mtd: pxa3xx: Add "marvell,nand-force-csx" compatible string" Not necessary to create a new compatible string. * "mtd-nand-pxa3xx-Set-FORCE_CSX-bit-to-ARMADA370-variants" Modified commit message. This commit sets the FORCE_CSX bit for all ARMADA370 variants. ---- Kalyan Kinthada (1): mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants. drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.14.1