Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753078AbdI0JEB (ORCPT ); Wed, 27 Sep 2017 05:04:01 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51492 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752507AbdI0JBZ (ORCPT ); Wed, 27 Sep 2017 05:01:25 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 76E8F6071D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org From: Manu Gautam To: Kishon Vijay Abraham I Cc: Felipe Balbi , linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Manu Gautam , Vivek Gautam , Viresh Kumar , Krzysztof Kozlowski , linux-kernel@vger.kernel.org (open list:GENERIC PHY FRAMEWORK) Subject: [PATCH v2 14/17] phy: qcom-qusb2: Set vbus sw-override signal in device mode Date: Wed, 27 Sep 2017 14:29:10 +0530 Message-Id: <1506502753-27408-15-git-send-email-mgautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506502753-27408-1-git-send-email-mgautam@codeaurora.org> References: <1506502753-27408-1-git-send-email-mgautam@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3557 Lines: 110 VBUS signal coming from PHY must be asserted in device for controller to start operation or assert pull-up. For some platforms where VBUS line is not connected to PHY there is HS_PHY_CTRL register in QSCRATCH wrapper that can be used by software to override VBUS signal going to controller. Signed-off-by: Manu Gautam --- drivers/phy/qualcomm/phy-qcom-qusb2.c | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c index bda1f4c..0e9d88b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c @@ -68,6 +68,11 @@ #define QUSB2PHY_IMP_CTRL2 0x224 #define QUSB2PHY_CHG_CTRL2 0x23c +/* QSCRATCH register bits */ +#define QSCRATCH_HS_PHY_CTRL 0x10 +#define UTMI_OTG_VBUS_VALID BIT(20) +#define SW_SESSVLD_SEL BIT(28) + struct qusb2_phy_init_tbl { unsigned int offset; unsigned int val; @@ -211,6 +216,7 @@ struct qusb2_phy_cfg { * * @phy: generic phy * @base: iomapped memory space for qubs2 phy + * @qscratch_base: iomapped memory space for qscratch region * * @cfg_ahb_clk: AHB2PHY interface clock * @ref_clk: phy reference clock @@ -223,10 +229,12 @@ struct qusb2_phy_cfg { * * @cfg: phy config data * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme + * @mode: indicate current PHY mode of operation e.g. HOST or DEVICE */ struct qusb2_phy { struct phy *phy; void __iomem *base; + void __iomem *qscratch_base; struct clk *cfg_ahb_clk; struct clk *ref_clk; @@ -239,6 +247,7 @@ struct qusb2_phy { const struct qusb2_phy_cfg *cfg; bool has_se_clk_scheme; + enum phy_mode mode; }; static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) @@ -307,6 +316,25 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) qusb2_setbits(qphy->base, QUSB2PHY_PORT_TUNE2, val[0] << 0x4); } +static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode) +{ + struct qusb2_phy *qphy = phy_get_drvdata(phy); + + qphy->mode = mode; + + /* Update VBUS override in qscratch register */ + if (qphy->qscratch_base) { + if (mode == PHY_MODE_USB_DEVICE) + qusb2_setbits(qphy->qscratch_base, QSCRATCH_HS_PHY_CTRL, + UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); + else + qusb2_clrbits(qphy->qscratch_base, QSCRATCH_HS_PHY_CTRL, + UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); + } + + return 0; +} + static int qusb2_phy_init(struct phy *phy) { struct qusb2_phy *qphy = phy_get_drvdata(phy); @@ -473,6 +501,7 @@ static int qusb2_phy_exit(struct phy *phy) static const struct phy_ops qusb2_phy_gen_ops = { .init = qusb2_phy_init, .exit = qusb2_phy_exit, + .set_mode = qusb2_phy_set_mode, .owner = THIS_MODULE, }; @@ -507,6 +536,16 @@ static int qusb2_phy_probe(struct platform_device *pdev) if (IS_ERR(qphy->base)) return PTR_ERR(qphy->base); + /* Check if platform uses qscratch wrapper */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qscratch"); + if (res) { + /* Can't request region as used by other phy and glue drivers */ + qphy->qscratch_base = devm_ioremap(dev, res->start, + resource_size(res)); + if (IS_ERR(qphy->qscratch_base)) + return PTR_ERR(qphy->qscratch_base); + } + qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); if (IS_ERR(qphy->cfg_ahb_clk)) { ret = PTR_ERR(qphy->cfg_ahb_clk); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project