Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753601AbdI0PQB (ORCPT ); Wed, 27 Sep 2017 11:16:01 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:37134 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753576AbdI0PP5 (ORCPT ); Wed, 27 Sep 2017 11:15:57 -0400 X-Google-Smtp-Source: AOwi7QBJO6FzeOntrerTu9DNpBJS1B83qlDFguCjbiQcyJKps+W67wMawBoe/gvcqNECBAnw9CEeUA== From: PrasannaKumar Muralidharan To: robh+dt@kernel.org, mark.rutland@arm.com, ralf@linux-mips.org, mturquette@baylibre.com, sboyd@codeaurora.org, devicetree@vger.kernel.org, linux-mips@linux-mips.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, paul@crapouillou.net, malat@debian.org, dom.peklo@gmail.com Cc: PrasannaKumar Muralidharan Subject: [RFC 1/4] dt-bindings: Add Ingenic X1000 SoC clock define Date: Wed, 27 Sep 2017 20:45:24 +0530 Message-Id: <20170927151527.25570-2-prasannatsmkumar@gmail.com> X-Mailer: git-send-email 2.10.0 In-Reply-To: <20170927151527.25570-1-prasannatsmkumar@gmail.com> References: <20170927151527.25570-1-prasannatsmkumar@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2480 Lines: 63 Ingenic X1000 SoC has different set of peripherals than JZ4780 and JZ4740. Add a new device tree binding for the clock. Signed-off-by: PrasannaKumar Muralidharan --- include/dt-bindings/clock/x1000-cgu.h | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 include/dt-bindings/clock/x1000-cgu.h diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h new file mode 100644 index 0000000..17f05bc --- /dev/null +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2016 PrasannaKumar Muralidharan + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ + +/* Add details for other peripherals when their support is added */ +#define X1000_CLK_EXCLK 0 +#define X1000_CLK_RTCLK (X1000_CLK_EXCLK + 1) +#define X1000_CLK_APLL (X1000_CLK_RTCLK + 1) +#define X1000_CLK_MPLL (X1000_CLK_APLL + 1) + +#define X1000_CLK_SCLKA (X1000_CLK_MPLL + 1) +#define X1000_CLK_CPUMUX (X1000_CLK_SCLKA + 1) +#define X1000_CLK_CPU (X1000_CLK_CPUMUX + 1) +#define X1000_CLK_L2CACHE (X1000_CLK_CPU + 1) +#define X1000_CLK_AHB0 (X1000_CLK_L2CACHE + 1) +#define X1000_CLK_AHB2PMUX (X1000_CLK_AHB0 + 1) +#define X1000_CLK_AHB2 (X1000_CLK_AHB2PMUX + 1) +#define X1000_CLK_PCLK (X1000_CLK_AHB2 + 1) +#define X1000_CLK_DDR (X1000_CLK_PCLK + 1) +#define X1000_CLK_MSCMUX (X1000_CLK_DDR + 1) +#define X1000_CLK_MSC0 (X1000_CLK_MSCMUX + 1) +#define X1000_CLK_MSC1 (X1000_CLK_MSC0 + 1) +#define X1000_CLK_CIMMCLK (X1000_CLK_MSC1 + 1) +#define X1000_CLK_PCMPLL (X1000_CLK_CIMMCLK + 1) +#define X1000_CLK_PCM (X1000_CLK_PCMPLL + 1) +#define X1000_CLK_NEMC (X1000_CLK_PCM + 1) +#define X1000_CLK_UART0 (X1000_CLK_NEMC + 1) +#define X1000_CLK_UART1 (X1000_CLK_UART0 + 1) +#define X1000_CLK_UART2 (X1000_CLK_UART1 + 1) +#define X1000_CLK_PDMA (X1000_CLK_UART2 + 1) +#define X1000_CLK_CIM (X1000_CLK_PDMA + 1) +#define X1000_CLK_DDR0 (X1000_CLK_CIM + 1) +#define X1000_CLK_DDR1 (X1000_CLK_DDR0 + 1) +#define X1000_CLK_CORE1 (X1000_CLK_DDR1 + 1) + +#define X1000_CLK_I2SPLL (X1000_CLK_CORE1 + 1) +#define X1000_CLK_I2S (X1000_CLK_I2SPLL + 1) + +#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ -- 2.10.0