Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752571AbdI1A6F (ORCPT ); Wed, 27 Sep 2017 20:58:05 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:52265 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752504AbdI1A6D (ORCPT ); Wed, 27 Sep 2017 20:58:03 -0400 From: Kalyan Kinthada To: dwmw2@infradead.org, computersforpeace@gmail.com, boris.brezillon@free-electrons.com, marek.vasut@gmail.com, richard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org, mark.rutland@arm.com, ezequiel.garcia@free-electrons.com, miquel.raynal@free-electrons.com, devicetree@vger.kernel.org Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, chris.packham@alliedtelesis.co.nz, Kalyan Kinthada Subject: [PATCH v3 0/1] Set FORCE_CSX bit when arbitration between NAND and NOR is enabled. Date: Thu, 28 Sep 2017 13:57:55 +1300 Message-Id: <20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz> X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1526 Lines: 43 When the arbitration between NOR and NAND flash is enabled the field bit[21] in the Data Flash Control Register needs to be set to 1 according to guidleine GL-5830741 mentioned in Marvell Errata document MV-S501377-00, Rev. D. Set the FORCE_CSX bit in NDCR for ARMADA370 variants as the arbitration is always enabled by default. This change does not apply for pxa3xx variants because FORCE_CSX bit does not exist/reserved on the NFCv1. Ran the "flash_speed" tool on NAND flash on a board with Armada-xp based SoC which uses only one NAND chip and not using the arbiter. There is no regression or speed penalty introduced due to this change. Changes since v2: Thanks Miquel RAYNAL for the suggestion. * "mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants." Modified commit message to mention that this change does not apply for pxa3xx variants. Fixed the missing space in comments. Removed unused macros "NDCR_ND_MODE" and "NDCR_NAND_MODE". Changes since v1: Thanks Miquel RAYNAL for the suggestion. * Deleted: "dt-bindings: mtd: pxa3xx: Add "marvell,nand-force-csx" compatible string" Not necessary to create a new compatible string. * "mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants." Modified commit message. This commit sets the FORCE_CSX bit for all ARMADA370 variants. ----- Kalyan Kinthada (1): mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants. drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.14.1