Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752760AbdI1J1M (ORCPT ); Thu, 28 Sep 2017 05:27:12 -0400 Received: from mga07.intel.com ([134.134.136.100]:56668 "EHLO mga07.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751088AbdI1J1K (ORCPT ); Thu, 28 Sep 2017 05:27:10 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,449,1500966000"; d="scan'208";a="1019374746" Date: Thu, 28 Sep 2017 15:01:04 +0530 From: Vinod Koul To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , Laxman Dewangan , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver Message-ID: <20170928093104.GC30097@localhost> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 722 Lines: 17 On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote: > NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels, > supports AHB <-> Memory and Memory <-> Memory transfers, slave / master > modes. This driver is primarily supposed to be used by gpu/host1x in a > master mode, performing 3D HW context stores. > > Dmitry Osipenko (5): > clk: tegra: Add AHB DMA clock entry > clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20 > dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller > dmaengine: Add driver for NVIDIA Tegra AHB DMA controller > ARM: dts: tegra: Add AHB DMA controller nodes I don't think they are dependent, so consider sending them separately -- ~Vinod