Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753319AbdI1PBo (ORCPT ); Thu, 28 Sep 2017 11:01:44 -0400 Received: from mga01.intel.com ([192.55.52.88]:16561 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752506AbdI1PBm (ORCPT ); Thu, 28 Sep 2017 11:01:42 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,450,1500966000"; d="scan'208";a="156599517" Date: Thu, 28 Sep 2017 08:01:36 -0700 (PDT) From: matthew.gerlach@linux.intel.com X-X-Sender: mgerlach@mgerlach-VirtualBox To: Vignesh R cc: Marek Vasut , Cyrille Pitchen , David Woodhouse , Brian Norris , Boris Brezillon , Rob Herring , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel Subject: Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support In-Reply-To: <7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com> Message-ID: References: <20170924105924.23923-1-vigneshr@ti.com> <20170924105924.23923-6-vigneshr@ti.com> <3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com> <4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com> <038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com> <7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: multipart/mixed; BOUNDARY="8323329-1557128041-1506610898=:2488" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2518 Lines: 77 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-1557128041-1506610898=:2488 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8BIT Hi Vignesh, I tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi kernel, and it did not go well. Commands to the flash chip timedout resulting in the probe function failing. I ran into other problems, not related to cadence-quadspi, that prevented me from testing against 4.9 and 4.12 kernels, but I suspect similar behavior. Matthew Gerlach On Wed, 27 Sep 2017, Vignesh R wrote: > Hi Matthew, > > On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote: > [...] >>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls. >>>> >>>> Not of the top of my head, sorry. +CC Matthew, he should know. >>> >>> I am not an expert at the clock framework nor the power management, but I >>> did ask around a bit.  No one I asked was planning to change the clk_*() >>> calls to pm_*() call, but the feedback was that it would be a good idea. >> >> The question is, if we do the replacement, will it break on socfpga ? >> A quick test might be useful. >> > > yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls > like below patch would be helpful: > > > diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c > index 53c7d8e0327a..7ad3e176cc88 100644 > --- a/drivers/mtd/spi-nor/cadence-quadspi.c > +++ b/drivers/mtd/spi-nor/cadence-quadspi.c > @@ -34,6 +34,7 @@ > #include > #include > #include > +#include > > #define CQSPI_NAME "cadence-qspi" > #define CQSPI_MAX_CHIPSELECT 16 > @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev) > return -ENXIO; > } > > - ret = clk_prepare_enable(cqspi->clk); > - if (ret) { > - dev_err(dev, "Cannot enable QSPI clock.\n"); > - return ret; > - } > + pm_runtime_enable(dev); > + pm_runtime_get_sync(dev); > > cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); > > > > > > -- > Regards > Vignesh > --8323329-1557128041-1506610898=:2488--