Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932100AbdI1P1A (ORCPT ); Thu, 28 Sep 2017 11:27:00 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:49771 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753367AbdI1P06 (ORCPT ); Thu, 28 Sep 2017 11:26:58 -0400 Date: Thu, 28 Sep 2017 17:26:46 +0200 From: Maxime Ripard To: Stefan =?iso-8859-1?Q?Br=FCns?= Cc: linux-sunxi@googlegroups.com, devicetree@vger.kernel.org, Chen-Yu Tsai , Andre Przywara , linux-kernel@vger.kernel.org, Dan Williams , Vinod Koul , Rob Herring , dmaengine@vger.kernel.org, Code Kipper , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Mark Rutland Subject: Re: [PATCH v4 00/11] dmaengine: sun6i: Fixes for H3/A83T, enable A64 Message-ID: <20170928152646.jteewxaqqbkw777s@flea> References: <3c78e966-2ece-4e67-94de-801aa569089f@rwthex-w2-a.rwth-ad.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="zmuabj2gnergbqcl" Content-Disposition: inline In-Reply-To: <3c78e966-2ece-4e67-94de-801aa569089f@rwthex-w2-a.rwth-ad.de> User-Agent: NeoMutt/20170914 (1.9.0) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3032 Lines: 83 --zmuabj2gnergbqcl Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Sep 28, 2017 at 01:49:17AM +0000, Stefan Br=FCns wrote: > Commit 3a03ea763a67 ("dmaengine: sun6i: Add support for Allwinner A83T > (sun8i) variant") and commit f008db8c00c1 ("dmaengine: sun6i: Add support= for > Allwinner H3 (sun8i) variant") added support for the A83T resp. H3, but m= issed > some differences between the original A31 and A83T/H3. >=20 > The first patch adds a callback to the controller config to set the clock > autogating register of different SoC generations, i.e. A31, A23+A83T, H3+= later, > and uses it to for the correct clock autogating setting. >=20 > The second patch adds a callback for the burst length setting in the chan= nel > config register, which has different field offsets and new burst widths/l= engths, > which differs between H3 and earlier generations >=20 > The third patch restructures some code required for the fourth patch and = adds the > burst lengths to the controller config. >=20 > The fourth patch adds the burst widths to the config and adds the handlin= g of the > H3 specific burst widths. >=20 > Patch 5 restructures the code to decouple some controller details (e.g. c= hannel > count) from the compatible string/the config. >=20 > Patches 6, 7 and 8 introduce and use the "dma-chans" property for the A64= =2E Although > register compatible to the H3, the channel count differs and thus it requ= ires a > new compatible. To avoid introduction of new compatibles for each minor v= ariation, > anything but the register model is moved to devicetree properties. There > is at least one SoC (R40) which can then reuse the A64 compatible, the sa= me > would have worked for A83T+V3s. >=20 > Patches 9 and 10 add the DMA controller node to the devicetree and add th= e DMA > controller reference to the SPI nodes. >=20 > Patch 11 fixes a small error in the devicetree binding example. Applied patches 9-11, thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --zmuabj2gnergbqcl Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBAgAGBQJZzRS2AAoJEBx+YmzsjxAgUDcP/i98qXuTV3oUVkapT5lgZf+Z 87m/BVBTXBkH617tizXtt/d8a9S1V1WSB/jfMUPaKolsu+4dcNmswr/yt8qOUEha 1KCYW8+pXrwE4yNRU5cHD4/jOClmmG7cvIKOKY8TjZXuzWV/PFkPfmVjmqr80nnH C0UKDGA7prm+meXh6JRg/WZE8sY+OgusJ6cCF/Pvl1uPB/n3o+8wFe8uZOVPqH7M jpYe3jsiwVe0+eby30DO7roVcs+KoGQBTzY74vEwcYbTCsNJM2ovEDXYT/ssRung 36X45YJyGzOg+a2DcCaSEqOq9iWwk8eDsUnXcAafl1l/dKEdinOFTctIigBgojSK qADerRwfJLmMxgpdcycDQSwxa29Pyy7SyZDMw76DfW46C1kFty0kbUwoKC71E176 dmDX0uR8UM4mdPPBtGTRJ3zCf7+8wgtOLYJDtk2IzQ/KdTB+iUq4i+keX89JFf1k MIzqocWCYI6aslCOsb8cZXeZhBV3JoQM0PNnrQ6MxtOHBB8gfEE+MVbrW/64a9d5 oOLLUCBrqLTfaDUDORkK/fr6rLJDZGexPam8rx2Cu3LbP81UsE40Sf4WbaaCIr1L QjX3xunHCjXkjBTTkIpChiyBdQt4ThODpbjnzbwdfsrLo2ggBNnNxqyjghtbdAKC n2TqhBAZACo9s9BwBaxT =U705 -----END PGP SIGNATURE----- --zmuabj2gnergbqcl--