Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752737AbdI1Rwn (ORCPT ); Thu, 28 Sep 2017 13:52:43 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51032 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752094AbdI1Rvl (ORCPT ); Thu, 28 Sep 2017 13:51:41 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6BB3360C16 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu Subject: [PATCH 11/13] clk: qcom: support for Brammo PLL Date: Thu, 28 Sep 2017 23:20:48 +0530 Message-Id: <1506621050-10129-12-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2007 Lines: 58 1. Brammo PLL does not allow configuration of VCO 2. Supports the dynamic update in which the frequency can be changed dynamically without turning off the PLL 3. The register offsets are different from normal Alpha PLL Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 24 ++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4844e63..c682387 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -922,4 +922,28 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, .set_rate = alpha_pll_huayra_set_rate, }, }, + [CLK_ALPHA_PLL_TYPE_BRAMMO] = { + .reg_offsets = { + [PLL_L_VAL] = 0x04, + [PLL_ALPHA_VAL] = 0x08, + [PLL_ALPHA_VAL_U] = 0x0c, + [PLL_USER_CTL] = 0x10, + [PLL_CONFIG_CTL] = 0x18, + [PLL_TEST_CTL] = 0x1c, + [PLL_STATUS] = 0x24, + }, + .alpha_width = 40, + .flags = SUPPORTS_DYNAMIC_UPDATE, + .ops = { + .enable = alpha_pll_default_enable, + .disable = alpha_pll_default_disable, + .is_enabled = alpha_pll_default_is_enabled, + .hwfsm_enable = alpha_pll_default_hwfsm_enable, + .hwfsm_disable = alpha_pll_default_hwfsm_disable, + .hwfsm_is_enabled = alpha_pll_default_hwfsm_is_enabled, + .recalc_rate = alpha_pll_default_recalc_rate, + .round_rate = alpha_pll_default_round_rate, + .set_rate = alpha_pll_default_set_rate, + }, + }, }; diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index fed783e..dee71b4 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -21,6 +21,7 @@ enum { CLK_ALPHA_PLL_TYPE_DEFAULT, CLK_ALPHA_PLL_TYPE_HUAYRA, + CLK_ALPHA_PLL_TYPE_BRAMMO, CLK_ALPHA_PLL_TYPE_MAX, }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation