Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752639AbdI1Ry5 (ORCPT ); Thu, 28 Sep 2017 13:54:57 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:50310 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752405AbdI1RvH (ORCPT ); Thu, 28 Sep 2017 13:51:07 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org D6E5E60AD5 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=absahu@codeaurora.org From: Abhishek Sahu To: Stephen Boyd , Michael Turquette Cc: Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Abhishek Sahu Subject: [PATCH 02/13] clk: qcom: minor code reorganization related with offset variable Date: Thu, 28 Sep 2017 23:20:39 +0530 Message-Id: <1506621050-10129-3-git-send-email-absahu@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2755 Lines: 94 This patch does minor code reorganization related with offset variable assignment. The offset variable can be directly defined which will help in subsequent patches to support different PLL offset registers. Signed-off-by: Abhishek Sahu --- drivers/clk/qcom/clk-alpha-pll.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index b9be822..ab2f23c 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -70,12 +70,11 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, const char *action) { - u32 val, off; + u32 val, off = pll->offset; int count; int ret; const char *name = clk_hw_get_name(&pll->clkr.hw); - off = pll->offset; ret = regmap_read(pll->clkr.regmap, off, &val); if (ret) return ret; @@ -143,11 +142,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) { - int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + int ret; + u32 val, off = pll->offset; - off = pll->offset; ret = regmap_read(pll->clkr.regmap, off, &val); if (ret) return ret; @@ -169,11 +167,10 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) { - int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + int ret; + u32 val, off = pll->offset; - off = pll->offset; ret = regmap_read(pll->clkr.regmap, off, &val); if (ret) return; @@ -200,11 +197,10 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw) static int pll_is_enabled(struct clk_hw *hw, u32 mask) { - int ret; - u32 val, off; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + int ret; + u32 val, off = pll->offset; - off = pll->offset; ret = regmap_read(pll->clkr.regmap, off, &val); if (ret) return ret; @@ -226,9 +222,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw) { int ret; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 val, mask, off; - - off = pll->offset; + u32 val, mask, off = pll->offset; mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; ret = regmap_read(pll->clkr.regmap, off, &val); @@ -280,9 +274,7 @@ static void clk_alpha_pll_disable(struct clk_hw *hw) { int ret; struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 val, mask, off; - - off = pll->offset; + u32 val, mask, off = pll->offset; ret = regmap_read(pll->clkr.regmap, off, &val); if (ret) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation