Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752510AbdI2TTX convert rfc822-to-8bit (ORCPT ); Fri, 29 Sep 2017 15:19:23 -0400 Received: from esa1.microchip.iphmx.com ([68.232.147.91]:12556 "EHLO esa1.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752294AbdI2TTV (ORCPT ); Fri, 29 Sep 2017 15:19:21 -0400 X-IronPort-AV: E=Sophos;i="5.42,453,1500966000"; d="scan'208";a="7874464" From: To: CC: , , , , , , , , Subject: RE: [PATCH RFC 3/5] Add KSZ8795 switch driver Thread-Topic: [PATCH RFC 3/5] Add KSZ8795 switch driver Thread-Index: AdMoGw7chwKpH5nHQDyZLhGSoYClOwAA0svAABGDyIACFLHiAAIFED0AAByk3AAABjO4gAAC/4VwAAsD8AAADnmeYA== Date: Fri, 29 Sep 2017 19:19:17 +0000 Message-ID: <93AF473E2DA327428DE3D46B72B1E9FD4112CC1D@CHN-SV-EXMX02.mchp-main.com> References: <93AF473E2DA327428DE3D46B72B1E9FD41121A87@CHN-SV-EXMX02.mchp-main.com> <20170907223625.GW11248@lunn.ch> <93AF473E2DA327428DE3D46B72B1E9FD41124D5A@CHN-SV-EXMX02.mchp-main.com> <20170928193416.GH14940@lunn.ch> <063D6719AE5E284EB5DD2968C1650D6DD0084EDC@AcuExch.aculab.com> <20170929121201.GD19710@lunn.ch> <93AF473E2DA327428DE3D46B72B1E9FD4112CB89@CHN-SV-EXMX02.mchp-main.com> <20170929185316.GB17713@lunn.ch> In-Reply-To: <20170929185316.GB17713@lunn.ch> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.10.76.4] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1031 Lines: 21 > > My concern is if a task is already running with SPI access to a lot > > of registers like reading the 32 MIB counters in every port of the > > switch, another register access has to wait until they are finished. > > Why does it have to wait? Looking at the code in > ksz_get_ethtool_stats(), you don't take any mutex which will prevent > others from using the SPI bus. All there is is a mutex which prevents > two sets of ksz_get_ethtool_stats() at the same time. > > So a PTP read could happen in parallel, and will not be blocked by MIB > reads. They should get interleaved access to the SPI bus. > The MIB counters are read in the background. For multiple CPU cores 2 tasks may run in the same time allowing SPI access one after another. For single core I am not sure an SPI access like coming from an interrupt routine can jump ahead from one in a background task. I know nowadays SoCs are powerful enough to do amazing things. It is just I spent a long time using a low-powered SoC doing switch driver development.