Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752498AbdLAMZI (ORCPT ); Fri, 1 Dec 2017 07:25:08 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:39384 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752195AbdLAMZG (ORCPT ); Fri, 1 Dec 2017 07:25:06 -0500 Date: Fri, 1 Dec 2017 13:25:02 +0100 From: Sebastian Reichel To: Tomi Valkeinen Cc: Tony Lindgren , Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCHv1 03/14] drm/omap: plane: update fifo size on ovl setup Message-ID: <20171201122502.ynl3aubhsoiatfby@earth> References: <20170724173311.27170-1-sebastian.reichel@collabora.co.uk> <20170724173311.27170-4-sebastian.reichel@collabora.co.uk> <34c2588e-7d7e-219f-fd34-9a441d46e0cc@ti.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="loywtm66zg2dfhmr" Content-Disposition: inline In-Reply-To: <34c2588e-7d7e-219f-fd34-9a441d46e0cc@ti.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3567 Lines: 95 --loywtm66zg2dfhmr Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Tomi, On Fri, Dec 01, 2017 at 02:10:42PM +0200, Tomi Valkeinen wrote: >=20 > On 24/07/17 20:33, Sebastian Reichel wrote: > > This is a workaround for a hardware bug occuring on OMAP3 > > with manually updated panels. Details about the HW bug are > > unknown to me, but without this fix the panel refresh does > > not work at all on Nokia N950. > >=20 > > Signed-off-by: Sebastian Reichel > > --- > > drivers/gpu/drm/omapdrm/dss/dispc.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omap= drm/dss/dispc.c > > index fd7504b37e3b..b6dca5ee34d4 100644 > > --- a/drivers/gpu/drm/omapdrm/dss/dispc.c > > +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c > > @@ -1398,6 +1398,18 @@ void dispc_ovl_compute_fifo_thresholds(enum omap= _plane_id plane, > > } > > } > > =20 > > +void dispc_ovl_set_manual_fifo_threshold(enum omap_plane_id plane) > > +{ > > + u32 fifo_low, fifo_high; > > + bool use_fifo_merge =3D false; > > + bool use_manual_update =3D true; > > + > > + dispc_ovl_compute_fifo_thresholds(plane, &fifo_low, &fifo_high, > > + use_fifo_merge, use_manual_update); > > + > > + dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high); > > +} > > + > > static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable) > > { > > int bit; > > @@ -2566,6 +2578,10 @@ static int dispc_ovl_setup(enum omap_plane_id pl= ane, > > oi->zorder, oi->pre_mult_alpha, oi->global_alpha, > > oi->rotation_type, replication, vm, mem_to_mem); > > =20 > > + /* manual mode needs other fifo thresholds */ > > + if (mgr_fld_read(channel, DISPC_MGR_FLD_STALLMODE)) > > + dispc_ovl_set_manual_fifo_threshold(plane); > > + > > return r; > > } >=20 > We don't have the stallmode for all channels. And on OMAP2 it's for > RFBI, and I don't know if that needs different thresholds or not. Also, > I'm not sure if OMAP4-5 DSI needs this. And I think it's good to mention > the unknown bug in the comment too. And yes, it's unknown to me too, I > never figured it out. These thresholds just seemed to work, while the > default did not. >=20 > So I think we need to check that the platform is OMAP3 and channel is > LCD. We can later extend that to cover OMAP4-5 if needed. Ok. I will have a look at this later today. FWIW I test this patchset with OMAP3 (N950) and OMAP4 (Droid 4). OMAP4 works without this patch, but also with the changed thresholds. -- Sebastian --loywtm66zg2dfhmr Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAlohShMACgkQ2O7X88g7 +ppfBg//ZLhUaDvPQ9RTsu3o1na/8pBM/vTa9vnDHHopzptw00YDS4f+IBoxRInq ja4bbPe0JcweGyY2+ZoywAAGS+JH7OR8pv6nbGFyM9R92YPKfANVphPB5kDrKg/+ h5c+4ogUKu8ezDNtMdcu8ZoD45bk/gTOzYJFhBgpWA8JYBZ2JxBPL918U5OrjySC PCO4jLcc+9zjbZiIIjf+14MlUNtdJpUJrasdUVzQS1v2oPpk4lCGiy64wNWtpjAU KVVtws/hiCyDpPFD1QNGx+Z0TtKAEyOYaLUJldvtMwzm//+SGuDkg6jmJM9J0wFp fIwPfsettkiXMk2yFcsweEBVtaNKDpee8H4xsHMux29qvO+azLv4V7ydYlGqYwsQ i3iCklgzAay6uGgp18jQHzVZE9+/dvWIDbhBH7x7hpDyBvriHDTahmMYwHgYl5ig LOyET979SiSyYdQIB9Hr9XpcJn9s/dZBLFv2O063EEExDh3JThq02rKId+kpXbmv n3iJWzzvucka64GFD8chzWyH58dUCVl/zjYeTQad2e3tYz/suzDesA9Z8l3Xde96 F8U9315d17yFITUWmnfQN9K+mk2oB+jsZOmR4fHlru6t10+MA9GdCCPgxPmw+BMO 1pwxa5dYlORvMKKDiaGfwHrNBsMY2PG/XsgwKrI64Lb+Gz7I6O0= =eAqg -----END PGP SIGNATURE----- --loywtm66zg2dfhmr--