Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753603AbdLDQE7 (ORCPT ); Mon, 4 Dec 2017 11:04:59 -0500 Received: from webbox1416.server-home.net ([77.236.96.61]:34215 "EHLO webbox1416.server-home.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752761AbdLDQEu (ORCPT ); Mon, 4 Dec 2017 11:04:50 -0500 From: Alexander Stein To: Marc Zyngier Cc: Rasmus Villemoes , LKML , Thomas Gleixner , Shawn Guo Subject: Re: polarity inversion on LS1021a Date: Mon, 04 Dec 2017 17:04:44 +0100 Message-ID: <6588111.hDmIEKzSZ3@ws-stein> In-Reply-To: <4f27f4e1-f42c-e931-a31b-067bb62eed77@arm.com> References: <67135504-72fb-ef7e-cac4-03331550a38d@prevas.dk> <2780635.GsDK2O7NgM@ws-stein> <4f27f4e1-f42c-e931-a31b-067bb62eed77@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1627 Lines: 32 On Monday, December 4, 2017, 4:37:20 PM CET Marc Zyngier wrote: > On 04/12/17 15:31, Alexander Stein wrote: > > On Monday, December 4, 2017, 4:11:06 PM CET Rasmus Villemoes wrote: > >> The LS1021A has a standard GIC-400, but allows inverting the polarity of > >> six external interrupt lines via a certain register, effectively > >> supporting IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. > >> > >> I'm trying to figure out how one would add support for this. The patch > >> below works but is obviously just meant to help show what I mean, so > >> please don't comment on all the things that are wrong with it. > >> > >> It feels wrong to create a whole new irqchip driver copy-pasting the > >> entire irg-gic.c, but I can't figure out how and where one could hook > >> into the existing one. Any pointers on how to do this properly will be > >> greatly appreciated. > > > > In my opinion a new irqchip is still required, but solely for modifying > > SCFG_INTPCR depending on IRQ_TYPE_* > > You would need to insert it as a cascading interrupt chip in device tree. > > You also need to protect accesses to this register using a spinlock. > > This is at least my idea how I would have done it, though never got time > > for it. > Almost. See my earlier reply. You just need a very minimal driver that > only takes care of the polarity thing. Nobody needs to see yet another > GIC driver... Ah, maybe I should have made that more clear. Of course only a rather simple driver for that single register is needed. The driver needs to handle the infamous big-little-endian mismatch in ls1021a. Best regards, Alexander