Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753000AbdLEI6B (ORCPT ); Tue, 5 Dec 2017 03:58:01 -0500 Received: from mail-qt0-f195.google.com ([209.85.216.195]:33953 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752633AbdLEI57 (ORCPT ); Tue, 5 Dec 2017 03:57:59 -0500 X-Google-Smtp-Source: AGs4zMYfqHm7T1AZzodWMugVFVmmbEq7W3veS5GUbEGzS+WHn+le5cduGi3QfGICaWIU+X157Ebn/NNLNl9v0nQZYqw= MIME-Version: 1.0 In-Reply-To: <20171204211705.543xjzvttbrt65pm@rob-hp-laptop> References: <1512048586-17534-1-git-send-email-geert+renesas@glider.be> <1512048586-17534-2-git-send-email-geert+renesas@glider.be> <20171204211705.543xjzvttbrt65pm@rob-hp-laptop> From: Geert Uytterhoeven Date: Tue, 5 Dec 2017 09:57:58 +0100 X-Google-Sender-Auth: TL3t6nLiadXhLPzcU6Xnc5bjE54 Message-ID: Subject: Re: [PATCH 1/3] eeprom: at25: Add DT support for EEPROMs with odd address bits To: Rob Herring Cc: Ivo Sieben , Arnd Bergmann , Greg Kroah-Hartman , Mark Rutland , Chris Wright , Wolfram Sang , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2212 Lines: 55 Hi Rob, On Mon, Dec 4, 2017 at 10:17 PM, Rob Herring wrote: > On Mon, Dec 04, 2017 at 10:17:47AM +0100, Geert Uytterhoeven wrote: >> On Thu, Nov 30, 2017 at 2:29 PM, Geert Uytterhoeven >> wrote: >> > Certain EEPROMS have a size that is larger than the number of address >> > bytes would allow, and store the MSB of the address in bit 3 of the >> > instruction byte. >> > >> > This can be described in platform data using EE_INSTR_BIT3_IS_ADDR, or >> > in DT using the obsolete legacy "at25,addr-mode" property. >> > But currently there exists no non-deprecated way to describe this in DT. >> > >> > Hence extend the existing "address-width" DT property to allow >> > specifying 9, 17, or 25 address bits, and enable support for that in the >> > driver. >> > >> > Signed-off-by: Geert Uytterhoeven >> > --- >> > EEPROMs using 9 address bits are common (e.g. M95040, 25AA040/25LC040). >> > Do EEPROMs using 17 or 25 address bits, as mentioned in >> > include/linux/spi/eeprom.h, really exist? >> > Or should we just limit it to a single odd value (9 bits)? >> >> At least for the real Atmel parts, only the AT25040 part uses odd (8 + >> 1 bit) addressing. > > Seems like we should have a specific compatible for it. Possibly. But currently all configuration is done through DT properties, not through matching on compatible values. >> AT25M01 uses 3-byte addressing (it needs 17 bits). > > Do you need to know it is 17-bit vs. 24-bits? I'm guessing not as the > unused bits are probably don't care. The 17 bits can be derived from the EEPROM size in bytes (1 Mb = 128 KiB). What is important to know is how to pass addresses to the device: 1. 3 address bytes, OR 2. 2 address bytes, and the odd MSB bit in the command byte. But apparently the second scheme is not used for 17-bit addressing. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds