Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752559AbdLFGBn (ORCPT ); Wed, 6 Dec 2017 01:01:43 -0500 Received: from mail-cys01nam02on0074.outbound.protection.outlook.com ([104.47.37.74]:39424 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752176AbdLFGBm (ORCPT ); Wed, 6 Dec 2017 01:01:42 -0500 From: Dhaval Rajeshbhai Shah To: "'Greg KH'" CC: "arnd@arndb.de" , "linux-kernel@vger.kernel.org" , "michal.simek@xilinx.com" , Hyun Kwon Subject: RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver Thread-Topic: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver Thread-Index: AQHTbb/vvsNWt82zs0iPUUhWqjiWdqM0vs4AgAERK+A= Date: Wed, 6 Dec 2017 06:01:37 +0000 Message-ID: References: <1512474212-12803-1-git-send-email-dshah@xilinx.com> <20171205133002.GB13746@kroah.com> In-Reply-To: <20171205133002.GB13746@kroah.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=DSHAH@xilinx.com; x-originating-ip: [149.199.62.254] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM2PR0201MB1007;6:SfnC8WeNFSz/KsuGlcUInBwvr7i8GSHTMa0ljJ7acXUunuuupwfpuFgS5TerDLefxhWJYOI8VrJhG8qNvxq6Q4Lz5M/TBOtx9rfmvFw2Dt7yZtjsuXH2dzEDpDJl8VNi2nWZrK6KzefzDvoZzpUb3N0DENt6EQ6VJAYkiGoflfOOWjqGJNJnghS3z1NqBTHz39IES4cmOx+m0aJPwvflttVekkTPwecaoYWoVysPnFsD1gCrBK0ubltWVgqCXQjt5mPMWF5l7MswMxnQWilXtpjmPkVpdCgW08YrW+kcCL4irzGwZXfxbEBgyQwpPciOufNXZtNlYXy4gBifBN2AO184cpGLLW904VJeEy4NGAE=;5:BQvkPbZtMW3KccZa10wIMaveM+Foc0Lh7MUtEEFnOXEcKWt0jD8dciEihSOjsnUuqvb3WRu4X8CK30O0kDujAbhyH6mmd+h+/F+BsUQUS7mPDSeBD+xWXEk+xp3Ts8P8LsUzKFDpOzSuTTt7C9G5+r1Ipkq03em+uL3t0DeZb8s=;24:Z2jUCnTQUxSyFgK+ZDlmsq8/zMjbMiC/8ksZdWueLTAsM0lQGTkBfK6V2oklaafEZTHmqI0Y2lqK8Y2vPzEWExa8mmeIr7U01ndGcv/gHG8=;7:m1H7qY+P7a3v0XnffgQZrajt/wojbAgEtwAPF+CX8WCpPR1pCL/WW+S7eJpqBRIhxTlptlnAoXKXd24Tr+rSPbjP6IxycJfy7elxJn+3rsSrr7FO67//8496+g3D4b74Ydf3MIsYhogVFdjEkV//cEH2QCcgogUWWgxFKzBWu0dkq/4ljRvKXNSLnLHK+2wSfPFageg/YcmystNuygXohFBa0EwsBpbjgqZpfsoUVpHAMHDt8fiHyI7o/uDL6LrD x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-forefront-antispam-report: SFV:SKI;SCL:-1;SFV:NSPM;SFS:(10009020)(346002)(366004)(376002)(43544003)(24454002)(13464003)(199004)(189003)(81166006)(81156014)(8676002)(3660700001)(4326008)(72206003)(478600001)(7736002)(305945005)(66066001)(68736007)(74316002)(33656002)(2900100001)(106356001)(25786009)(105586002)(3280700002)(14454004)(5660300001)(55016002)(6916009)(6506006)(99286004)(6436002)(9686003)(102836003)(229853002)(3846002)(77096006)(6116002)(53936002)(2950100002)(6246003)(107886003)(2906002)(7696005)(76176011)(8936002)(101416001)(316002)(97736004)(86362001)(54906003)(80792005)(53546010)(217873001);DIR:OUT;SFP:1101;SCL:1;SRVR:DM2PR0201MB1007;H:BY2PR0201MB1879.namprd02.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; x-ms-office365-filtering-correlation-id: 8c52ad11-2829-4134-1fef-08d53c6ecfd3 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(5600026)(4604075)(4534020)(4602075)(4627115)(201703031133081)(201702281549075)(48565401081)(2017052603286);SRVR:DM2PR0201MB1007; x-ms-traffictypediagnostic: DM2PR0201MB1007: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(9452136761055)(192813158149592); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040450)(2401047)(5005006)(8121501046)(3231022)(3002001)(10201501046)(93006095)(93001095)(6055026)(6041248)(20161123564025)(20161123558100)(20161123560025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123555025)(6072148)(201708071742011);SRVR:DM2PR0201MB1007;BCL:0;PCL:0;RULEID:(100000803101)(100110400095);SRVR:DM2PR0201MB1007; x-forefront-prvs: 05134F8B4F spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8c52ad11-2829-4134-1fef-08d53c6ecfd3 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Dec 2017 06:01:37.2644 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0201MB1007 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id vB661rg1023797 Content-Length: 3925 Lines: 107 Hi Greg k-h, Thanks a lot for the review. Replies inline. -----Original Message----- From: Greg KH [mailto:gregkh@linuxfoundation.org] Sent: Tuesday, December 05, 2017 5:30 AM To: Dhaval Rajeshbhai Shah Cc: arnd@arndb.de; linux-kernel@vger.kernel.org; michal.simek@xilinx.com; Hyun Kwon ; Dhaval Rajeshbhai Shah Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide the api which can be used by the > encoder and decoder driver to get the configured value. Your subject has a lot of [] in it, none of that is needed except the [PATCH] one :) [Dhaval ] : I will take care from next version. > > Signed-off-by: Dhaval Shah > --- > drivers/misc/Kconfig | 6 + > drivers/misc/Makefile | 1 + > drivers/misc/xlnx_vcu.c | 664 > ++++++++++++++++++++++++++++++++++++++++++++++++ > include/misc/xlnx_vcu.h | 18 ++ > 4 files changed, 689 insertions(+) > create mode 100644 drivers/misc/xlnx_vcu.c create mode 100644 > include/misc/xlnx_vcu.h > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index > f1a5c23..3b7c796 100644 > --- a/drivers/misc/Kconfig > +++ b/drivers/misc/Kconfig > @@ -496,6 +496,12 @@ config PCI_ENDPOINT_TEST > Enable this configuration option to enable the host side test driver > for PCI Endpoint. > > +config XILINX_VCU > + tristate "Xilinx VCU Init" > + default n That's always the default, no need for this. [Dhaval ] : I will remove that. > + help > + Driver for the Xilinx VCU Init based on the logicoreIP. You need a lot more help text here to explain what this driver is, what it is for, and who would need it. [Dhaval ] : I will provide more help text to provide more help on driver. Also, why is this a misc driver? [Dhaval ] : this driver is for the logicoreIP which is created to support the Processing system and Programmable logic isolation and to provide the clock related information. So this is not a VCU driver and but just a intermediate driver which supports logicoreIP. That's why no subsystem for this. > --- /dev/null > +++ b/drivers/misc/xlnx_vcu.c > @@ -0,0 +1,664 @@ > +/* > + * Xilinx VCU Init > + * > + * Copyright (C) 2016 - 2017 Xilinx, Inc. > + * > + * Contacts Dhaval Shah > + * > + * SPDX-License-Identifier: GPL-2.0 That line goes at the top of the file with // in front of it. [Dhaval ] : I will update that SPDX license as you said. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include Why do you need a .h file for a single driver? [Dhaval ] : There are few APIs and structure which are provided in the .h file which will be used by the other driver on the Xilinx based system. I have exported few API as well because of this reason. Those API will share the information from the logicoreIP register set. > +/** > + * xvcu_get_color_depth - read the color depth register > + * @xvcu: Pointer to the xvcu_device structure > + * > + * Return: Returns 32bit value > + * > + */ > +u32 xvcu_get_color_depth(struct xvcu_device *xvcu) { > + return xvcu_read(xvcu->logicore_reg_ba, VCU_ENC_COLOR_DEPTH); } > +EXPORT_SYMBOL_GPL(xvcu_get_color_depth); Why is your driver exporting symbols that no one uses? This feels very odd... [Dhaval ] : There are few information from the logicoreIp register set which needs to share with other driver. That's why those API are exported to use by other driver to get those information based on the requirement. greg k-h Regards, Dhaval