Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752593AbdLFLVU (ORCPT ); Wed, 6 Dec 2017 06:21:20 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:46686 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752561AbdLFLVO (ORCPT ); Wed, 6 Dec 2017 06:21:14 -0500 X-Google-Smtp-Source: AGs4zMZY2F3AFoJCDJWjBlZMb705keS4qq9S9hS1AxgJHyk2RfXKj6VusKuusuFDjomfHKEyyXv9uA== From: Jacob Chen To: linux-rockchip@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mchehab@kernel.org, linux-media@vger.kernel.org, sakari.ailus@linux.intel.com, hans.verkuil@cisco.com, tfiga@chromium.org, zhengsq@rock-chips.com, laurent.pinchart@ideasonboard.com, zyc@rock-chips.com, eddie.cai.linux@gmail.com, jeffy.chen@rock-chips.com, allon.huang@rock-chips.com, devicetree@vger.kernel.org, heiko@sntech.de, robh+dt@kernel.org, Joao.Pinto@synopsys.com, Luis.Oliveira@synopsys.com, Jose.Abreu@synopsys.com, Jacob Chen Subject: [PATCH v3 11/12] arm64: dts: rockchip: add rx0 mipi-phy for rk3399 Date: Wed, 6 Dec 2017 19:19:38 +0800 Message-Id: <20171206111939.1153-12-jacob-chen@iotwrt.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171206111939.1153-1-jacob-chen@iotwrt.com> References: <20171206111939.1153-1-jacob-chen@iotwrt.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1028 Lines: 34 From: Shunqian Zheng It's a Designware MIPI D-PHY, used for ISP0 in rk3399. Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 66a912fab5dd..a65b110afaf3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1292,6 +1292,17 @@ status = "disabled"; }; + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + bus-width = <4>; + status = "disabled"; + }; + u2phy0: usb2-phy@e450 { compatible = "rockchip,rk3399-usb2phy"; reg = <0xe450 0x10>; -- 2.15.0