Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754085AbdLGO3w (ORCPT ); Thu, 7 Dec 2017 09:29:52 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35508 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753762AbdLGO1W (ORCPT ); Thu, 7 Dec 2017 09:27:22 -0500 X-Google-Smtp-Source: AGs4zMa2e+kEkZ49c25g8LNwM1MT7A/zFfz93ZzQ7xcj7tOTgFIUiDMhhJVSCdudHnSfOcBQ6qBYOQ== From: Jerome Brunet To: Andrew Lunn , Florian Fainelli Cc: Jerome Brunet , Kevin Hilman , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v2 3/8] net: phy: meson-gxl: add read and write helpers for bank registers Date: Thu, 7 Dec 2017 15:27:10 +0100 Message-Id: <20171207142715.32578-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171207142715.32578-1-jbrunet@baylibre.com> References: <20171207142715.32578-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4130 Lines: 150 Add read and write helpers to manipulate banked registers on this PHY This helps clarify the settings applied to these registers in the init function and upcoming changes. Signed-off-by: Jerome Brunet --- drivers/net/phy/meson-gxl.c | 103 ++++++++++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 36 deletions(-) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index d82aa8cea401..05054770aefb 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -45,11 +45,13 @@ #define FR_PLL_DIV0 0x1c #define FR_PLL_DIV1 0x1d -static int meson_gxl_config_init(struct phy_device *phydev) +static int meson_gxl_open_banks(struct phy_device *phydev) { int ret; - /* Enable Analog and DSP register Bank access by */ + /* Enable Analog and DSP register Bank access by + * toggling TSTCNTL_TEST_MODE bit in the TSTCNTL register + */ ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; @@ -59,55 +61,84 @@ static int meson_gxl_config_init(struct phy_device *phydev) ret = phy_write(phydev, TSTCNTL, 0); if (ret) return ret; - ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); - if (ret) - return ret; + return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); +} - /* Write CONFIG_A6*/ - ret = phy_write(phydev, TSTWRITE, 0x8e0d) +static void meson_gxl_close_banks(struct phy_device *phydev) +{ + phy_write(phydev, TSTCNTL, 0); +} + +static int meson_gxl_read_reg(struct phy_device *phydev, + unsigned int bank, unsigned int reg) +{ + int ret; + + ret = meson_gxl_open_banks(phydev); if (ret) - return ret; - ret = phy_write(phydev, TSTCNTL, - TSTCNTL_WRITE - | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_ANALOG_DSP) - | TSTCNTL_TEST_MODE - | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, A6_CONFIG_REG)); + goto out; + + ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | + FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) | + TSTCNTL_TEST_MODE | + FIELD_PREP(TSTCNTL_READ_ADDRESS, reg)); if (ret) - return ret; + goto out; - /* Enable fractional PLL */ - ret = phy_write(phydev, TSTWRITE, 0x0005); + ret = phy_read(phydev, TSTREAD1); +out: + /* Close the bank access on our way out */ + meson_gxl_close_banks(phydev); + return ret; +} + +static int meson_gxl_write_reg(struct phy_device *phydev, + unsigned int bank, unsigned int reg, + uint16_t value) +{ + int ret; + + ret = meson_gxl_open_banks(phydev); if (ret) - return ret; - ret = phy_write(phydev, TSTCNTL, - TSTCNTL_WRITE - | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) - | TSTCNTL_TEST_MODE - | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_CONTROL)); + goto out; + + ret = phy_write(phydev, TSTWRITE, value); if (ret) - return ret; + goto out; - /* Program fraction FR_PLL_DIV1 */ - ret = phy_write(phydev, TSTWRITE, 0x029a); + ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | + FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) | + TSTCNTL_TEST_MODE | + FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg)); + +out: + /* Close the bank access on our way out */ + meson_gxl_close_banks(phydev); + return ret; +} + +static int meson_gxl_config_init(struct phy_device *phydev) +{ + int ret; + + /* Write CONFIG_A6*/ + ret = meson_gxl_write_reg(phydev, BANK_ANALOG_DSP, A6_CONFIG_REG, + 0x8e0d); if (ret) return ret; - ret = phy_write(phydev, TSTCNTL, - TSTCNTL_WRITE - | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) - | TSTCNTL_TEST_MODE - | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV1)); + + /* Enable fractional PLL */ + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_CONTROL, 0x5); if (ret) return ret; /* Program fraction FR_PLL_DIV1 */ - ret = phy_write(phydev, TSTWRITE, 0xaaaa); + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a); if (ret) return ret; - ret = phy_write(phydev, TSTCNTL, - TSTCNTL_WRITE - | FIELD_PREP(TSTCNTL_REG_BANK_SEL, BANK_BIST) - | TSTCNTL_TEST_MODE - | FIELD_PREP(TSTCNTL_WRITE_ADDRESS, FR_PLL_DIV0)); + + /* Program fraction FR_PLL_DIV1 */ + ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa); if (ret) return ret; -- 2.14.3