Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752436AbdLGXFt (ORCPT ); Thu, 7 Dec 2017 18:05:49 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:39828 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752291AbdLGXFr (ORCPT ); Thu, 7 Dec 2017 18:05:47 -0500 X-Google-Smtp-Source: AGs4zMbmOiow95OMsofy4g+usCvQj1/OE98NcQA0UUrzCgK6x6RBkEOHTnCNvB2Ed+f9Yr87GGxS0A== Subject: [PATCH v2] dt-bindings: Add an enable method to RISC-V Date: Thu, 7 Dec 2017 15:05:23 -0800 Message-Id: <20171207230523.29798-1-palmer@sifive.com> X-Mailer: git-send-email 2.13.6 Cc: devicetree@vger.kernel.org, patches@groups.riscv.org, linux-kernel@vger.kernel.org, Palmer Dabbelt From: Palmer Dabbelt To: robh+dt@kernel.org, mark.rutland@arm.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1796 Lines: 38 RISC-V doesn't currently specify a mechanism for enabling or disabling CPUs. Instead, we assume that all CPUs are enabled on boot, and if someone wants to save power we instead put a CPU to sleep via a WFI loop. Future systems may have an explicit mechanism for putting a CPU to sleep, so we're standardizing the device tree entry for when that happens. We're not defining a spin-table based interface to the firmware, as the plan is to handle this entirely within the kernel instead. CC: Mark Rutland Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/cpus.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af5dc3..68f88eacc594 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -82,6 +82,15 @@ described below. Value type: Definition: Contains the RISC-V ISA string of this hart. These ISA strings are defined by the RISC-V ISA manual. + - cpu-enable-method: + Usage: optional + Value type: + Definition: When absent, default is either "always-disabled" + "always-enabled", depending on the current state + of the CPU. + Must be one of: + * "always-disabled": This CPU cannot be enabled. + * "always-enabled": This CPU cannot be disabled. Example: SiFive Freedom U540G Development Kit --------------------------------------------- -- 2.13.6