Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754269AbdLHPuD (ORCPT ); Fri, 8 Dec 2017 10:50:03 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46824 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754337AbdLHPrq (ORCPT ); Fri, 8 Dec 2017 10:47:46 -0500 From: Alexandre Belloni To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , devicetree@vger.kernel.org, Sebastian Reichel , linux-pm@vger.kernel.org Subject: [PATCH v2 07/13] dt-bindings: power: reset: Document ocelot-reset binding Date: Fri, 8 Dec 2017 16:46:12 +0100 Message-Id: <20171208154618.20105-8-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171208154618.20105-1-alexandre.belloni@free-electrons.com> References: <20171208154618.20105-1-alexandre.belloni@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1172 Lines: 37 Add binding documentation for the Microsemi Ocelot reset block. Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: Sebastian Reichel Cc: linux-pm@vger.kernel.org Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt new file mode 100644 index 000000000000..1bcf276b04cb --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -0,0 +1,17 @@ +Microsemi Ocelot reset controller + +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the +SoC MIPS core. + +Required Properties: + - compatible: "mscc,ocelot-chip-reset" + +Example: + syscon@71070000 { + compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon"; + reg = <0x71070000 0x1c>; + + reset { + compatible = "mscc,ocelot-chip-reset"; + }; + }; -- 2.15.1