Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754421AbdLHPu4 (ORCPT ); Fri, 8 Dec 2017 10:50:56 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46817 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754332AbdLHPrp (ORCPT ); Fri, 8 Dec 2017 10:47:45 -0500 From: Alexandre Belloni To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v2 06/13] dt-bindings: mips: Add bindings for Microsemi SoCs Date: Fri, 8 Dec 2017 16:46:11 +0100 Message-Id: <20171208154618.20105-7-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171208154618.20105-1-alexandre.belloni@free-electrons.com> References: <20171208154618.20105-1-alexandre.belloni@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1891 Lines: 64 Add bindings for Microsemi SoCs. Currently only Ocelot is supported. Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/mips/mscc.txt | 46 +++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt new file mode 100644 index 000000000000..1bb578b9d135 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mscc.txt @@ -0,0 +1,46 @@ +* Microsemi MIPS CPUs + +Boards with a SoC of the Microsemi MIPS family shall have the following +properties: + +Required properties: +- compatible: "mscc,ocelot" +- mips-hpt-frequency: CPU counter frequency. + + +* Other peripherals: + +o CPU chip regs: + +The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous +functionalities: chip ID, general purpose register for software use, reset +controller, hardware status and configuration, efuses. + +Required properties: +- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon" +- reg : Should contain registers location and length + +Example: + syscon@71070000 { + compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon"; + reg = <0x71070000 0x1c>; + }; + + +o CPU system control: + +The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of +the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU +endianess, CPU bus control, CPU status. + +Required properties: +- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon" +- reg : Should contain registers location and length + +Example: + syscon@70000000 { + compatible = "mscc,ocelot-cpu-syscon", "syscon"; + reg = <0x70000000 0x2c>; + }; + + -- 2.15.1