Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754320AbdLHPrn (ORCPT ); Fri, 8 Dec 2017 10:47:43 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:46800 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754084AbdLHPrf (ORCPT ); Fri, 8 Dec 2017 10:47:35 -0500 From: Alexandre Belloni To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Alexandre Belloni , Thomas Gleixner , Jason Cooper Subject: [PATCH v2 02/13] dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller Date: Fri, 8 Dec 2017 16:46:07 +0100 Message-Id: <20171208154618.20105-3-alexandre.belloni@free-electrons.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171208154618.20105-1-alexandre.belloni@free-electrons.com> References: <20171208154618.20105-1-alexandre.belloni@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1714 Lines: 43 Add the Device Tree binding documentation for the Microsemi Ocelot interrupt controller that is part of the ICPU. It is connected directly to the MIPS core interrupt controller. Cc: Thomas Gleixner Cc: Jason Cooper Signed-off-by: Alexandre Belloni Acked-by: Rob Herring --- .../interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt new file mode 100644 index 000000000000..b47a8a02b17b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt @@ -0,0 +1,22 @@ +Microsemi Ocelot SoC ICPU Interrupt Controller + +Required properties: + +- compatible : should be "mscc,ocelot-icpu-intr" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; -- 2.15.1