Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754210AbdLIATI (ORCPT ); Fri, 8 Dec 2017 19:19:08 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:52152 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754088AbdLIAS6 (ORCPT ); Fri, 8 Dec 2017 19:18:58 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E19286084D Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Fri, 8 Dec 2017 16:18:55 -0800 From: Stephen Boyd To: Abhishek Sahu Cc: Michael Turquette , Andy Gross , David Brown , Rajendra Nayak , linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 03/13] clk: qcom: support for alpha pll properties Message-ID: <20171209001855.GL7997@codeaurora.org> References: <1506621050-10129-1-git-send-email-absahu@codeaurora.org> <1506621050-10129-4-git-send-email-absahu@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1506621050-10129-4-git-send-email-absahu@codeaurora.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1842 Lines: 48 On 09/28, Abhishek Sahu wrote: > Alpha PLL is a generic name used for QCOM PLL’s which uses L > and Alpha values for configuring the integer and fractional part. > QCOM SoC’s use different types of Alpha PLL’s for which basic > software configuration part is common with following differences. > > 1. All These PLL’s will have same basic registers like > PLL_MODE, L_VAL, ALPHA_VAL but some of the register offsets are > different in each PLL type. > 2. PLL dynamic programming sequence will be different in some > of the Alpha PLL’s > 3. Some of the PLL won’t have 64 bit config control, 64 bit > user control, VCO configuration etc. > > Now, this patch adds the Alpha PLL type in clock node and adds > alpha PLL properties structure inside clk-alpha-pll.c. This PLL > property will contain everything including register offsets, clock > operations and other properties since all these properties will be > fixed for Alpha PLL. > > This allows to support other types of Alpha PLL without addition > of new flag and variable in structures of clk_alpha_pll.h. Also, we > don’t have to add operation for each Alpha PLL’s and export them. > > In future, we can get rid of most of the flags like following > > struct clk_alpha_pll { > #define SUPPORTS_OFFLINE_REQ BIT(0) > #define SUPPORTS_16BIT_ALPHA BIT(1) > #define SUPPORTS_FSM_MODE BIT(2) > u8 flags; > }; > > struct clk_alpha_pll_postdiv { > u8 width; > }; > > Since all the above properties will be always same for different > instances of same type of Alpha PLL’s. > > Signed-off-by: Abhishek Sahu > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project