Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751359AbdLINu4 (ORCPT ); Sat, 9 Dec 2017 08:50:56 -0500 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9]:35333 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751228AbdLINuy (ORCPT ); Sat, 9 Dec 2017 08:50:54 -0500 From: Eugeniy Paltsev To: "sboyd@codeaurora.org" , "Alexey.Brodkin@synopsys.com" CC: "linux-kernel@vger.kernel.org" , "robh+dt@kernel.org" , "mturquette@baylibre.com" , "Eugeniy.Paltsev@synopsys.com" , "linux-snps-arc@lists.infradead.org" , "mark.rutland@arm.com" , "vladimir_zapolskiy@mentor.com" , "linux-clk@vger.kernel.org" Subject: Re: [PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree Thread-Topic: [PATCH RESEND] CLK: ARC: Set initial pll output frequency specified in device tree Thread-Index: AQHTXUL0do9T11iFGkC/rL2lVVShX6MUCSIAgABIHQCAACkdgIAmo8kA Date: Sat, 9 Dec 2017 13:50:49 +0000 Message-ID: <1512827448.2699.72.camel@synopsys.com> References: <20171114122020.9800-1-Eugeniy.Paltsev@synopsys.com> <1b07abf9-c94d-1759-4182-519b77c8bb37@mentor.com> <1510694373.15407.1.camel@synopsys.com> <20171114234643.GD11955@codeaurora.org> In-Reply-To: <20171114234643.GD11955@codeaurora.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.121.8.106] Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id vB9Dp4n7019226 Content-Length: 4820 Lines: 93 On Tue, 2017-11-14 at 15:46 -0800, sboyd@codeaurora.org wrote: > On 11/14, Alexey Brodkin wrote: > > Hi Vladimir, > > > > On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote: > > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote: > > > > > > > > Add option to set initial output frequency of plls via > > > > "clock-frequency" property in pll's device tree node. > > > > This frequency will be set while pll driver probed. > > > > > > > > The usage example is setting CPU clock frequency on boot > > > > See discussion: > > > > https://urldefense.proofpoint.com/v2/url?u=https-3A__www.mail-2Darchive.com_linux-2Dsnps-2Darc-40lists.infradead.org_msg02689.html&d=DwICAg&c= > > > > DPL6 > > > > _X_6JkXFx7AXWqB0tg&r=lqdeeSSEes0GFDDl656eViXO7breS55ytWkhpk5R81I&m=vTFoSv1E8NyQC8nqe6pwvuTDxGvEefhAdGwAoABOrY4&s=sbmMnczdKP317bN973cZn2WcYF29k > > > > VMLW > > > > chYfhSGT2M&e= > > > > > > > > Signed-off-by: Eugeniy Paltsev > > > > --- > > > >  .../bindings/clock/snps,hsdk-pll-clock.txt         |  5 ++++ > > > >  .../devicetree/bindings/clock/snps,pll-clock.txt   |  5 ++++ > > > >  drivers/clk/axs10x/pll_clock.c                     | 34 ++++++++++++++++++++-- > > > >  drivers/clk/clk-hsdk-pll.c                         | 34 ++++++++++++++++++++-- > > > >  4 files changed, 74 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > > > > index c56c755..5703059 100644 > > > > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > > > > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > > > > @@ -13,6 +13,10 @@ Required properties: > > > >  - clocks: shall be the input parent clock phandle for the PLL. > > > >  - #clock-cells: from common clock binding; Should always be set to 0. > > > >   > > > > +Optional properties: > > > > +- clock-frequency: output frequency generated by pll in Hz which will be set > > > > +while probing. Should be a single cell. > > > > + > > > >  Example: > > > >   input_clk: input-clk { > > > >   clock-frequency = <33333333>; > > > > @@ -25,4 +29,5 @@ Example: > > > >   reg = <0x00 0x10>; > > > >   #clock-cells = <0>; > > > >   clocks = <&input_clk>; > > > > + clock-frequency = <1000000000>; > > > >   }; > > > > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > > > > index 11fe487..5908f99 100644 > > > > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > > > > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > > > > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. > > > >  - clocks: shall be the input parent clock phandle for the PLL. > > > >  - #clock-cells: from common clock binding; Should always be set to 0. > > > >   > > > > +Optional properties: > > > > +- clock-frequency: output frequency generated by pll in Hz which will be set > > > > +while probing. Should be a single cell. > > > > + > > > >  Example: > > > >   input-clk: input-clk { > > > >   clock-frequency = <33333333>; > > > > @@ -25,4 +29,5 @@ Example: > > > >   reg = <0x80 0x10>, <0x100 0x10>; > > > >   #clock-cells = <0>; > > > >   clocks = <&input-clk>; > > > > + clock-frequency = <100000000>; > > > >   }; > > > > > > You may check Documentation/devicetree/bindings/clock/clock-bindings.txt > > > about how to assign initial clock rates, in general 'clock-frequency' > > > property is a property of clock consumers with two exceptions of simple > > > clock sources, namely it is used in fixed clock and PWM clock bindings. > > > > I think that's what we agreed on with Rob Herring back in the day. > > Have you checked this post of him on the topic? > > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002909.html&d=DwIDAw&c=DPL6_ > > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=yGJfHbjH2T75YeIJLB14_iDjfsKi1E5aaX > > Yu3QJBUIk&e= > > > > Just FYI it all started from my question here: > > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Dsnps-2Darc_2017-2DSeptember_002900.html&d=DwIDAw&c=DPL6_ > > X_6JkXFx7AXWqB0tg&r=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI&m=X0W8p5fOjiyVhK1216Lktb5yH3ojTSZhdnQhEiIVj0k&s=Jkzt2G_J4aE9JfePPQ57ldnrFWeS57Rhfc > > Mhun92oU0&e= > > Why can't we use assigned-clock-rates? That would basically call > clk_set_rate() on the clk once it's added. Thanks for the hint, assigned-clock-rates works for us. --  Eugeniy Paltsev