Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751365AbdLIN7Y (ORCPT ); Sat, 9 Dec 2017 08:59:24 -0500 Received: from smtprelay4.synopsys.com ([198.182.47.9]:35380 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751228AbdLIN7X (ORCPT ); Sat, 9 Dec 2017 08:59:23 -0500 From: Eugeniy Paltsev To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Vineet Gupta , Alexey Brodkin , Stephen Boyd , "robh+dt @ kernel . org" , Eugeniy Paltsev Subject: [PATCH 0/4] ARC: Set initial core pll output frequency via DTS Date: Sat, 9 Dec 2017 16:59:14 +0300 Message-Id: <20171209135918.16720-1-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 765 Lines: 19 Set initial core pll output frequency on HSDK and AXS103 via "assigned-clock-rates" property in device tree. It will be applied at the core pll driver probing. Eugeniy Paltsev (4): ARC: [plat-hsdk]: Set initial core pll output frequency ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code ARC: [plat-axs103]: Set initial core pll output frequency ARC: [plat-axs103] refactor the quad core DT quirk code arch/arc/boot/dts/axc003.dtsi | 3 +++ arch/arc/boot/dts/axc003_idu.dtsi | 3 +++ arch/arc/boot/dts/hsdk.dts | 3 +++ arch/arc/plat-axs10x/axs10x.c | 18 ++++++++--------- arch/arc/plat-hsdk/platform.c | 42 --------------------------------------- 5 files changed, 17 insertions(+), 52 deletions(-) -- 2.9.3