Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752355AbdLIOAE (ORCPT ); Sat, 9 Dec 2017 09:00:04 -0500 Received: from smtprelay.synopsys.com ([198.182.60.111]:52580 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751769AbdLIN7e (ORCPT ); Sat, 9 Dec 2017 08:59:34 -0500 From: Eugeniy Paltsev To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Vineet Gupta , Alexey Brodkin , Stephen Boyd , "robh+dt @ kernel . org" , Eugeniy Paltsev Subject: [PATCH 4/4] ARC: [plat-axs103] refactor the quad core DT quirk code Date: Sat, 9 Dec 2017 16:59:18 +0300 Message-Id: <20171209135918.16720-5-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171209135918.16720-1-Eugeniy.Paltsev@synopsys.com> References: <20171209135918.16720-1-Eugeniy.Paltsev@synopsys.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1448 Lines: 40 Refactor the quad core DT quirk code: get rid of waste division and multiplication by 1000000 constant. Signed-off-by: Eugeniy Paltsev --- arch/arc/plat-axs10x/axs10x.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index 28b3cb2..0ea2f86 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -324,19 +324,21 @@ static void __init axs103_early_init(void) * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack * of fudging the freq in DT */ +#define AXS103_QUAD_CORE_CPU_FREQ_HZ 50000000 + unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; if (num_cores > 2) { - u32 freq = 50, orig; + u32 freq; int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk"); const struct fdt_property *prop; prop = fdt_get_property(initial_boot_params, off, "assigned-clock-rates", NULL); - orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000; + freq = be32_to_cpu(*(u32 *)(prop->data)); /* Patching .dtb in-place with new core clock value */ - if (freq != orig ) { - freq = cpu_to_be32(freq * 1000000); + if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) { + freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ); fdt_setprop_inplace(initial_boot_params, off, "assigned-clock-rates", &freq, sizeof(freq)); } -- 2.9.3