Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752346AbdLJV62 (ORCPT ); Sun, 10 Dec 2017 16:58:28 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:45082 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751625AbdLJV60 (ORCPT ); Sun, 10 Dec 2017 16:58:26 -0500 X-Google-Smtp-Source: AGs4zMYGUkH6OszAlHd61sWWqFhmvC9UupupW/RN3oknPtQC31ak245LuRMF/dpQ01VhHBfC8Cik4g== Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (1.0) Subject: Re: [PATCH] Fix resume on x86-32 machines From: Andy Lutomirski X-Mailer: iPhone Mail (15C114) In-Reply-To: <20171210213804.GA4660@amd> Date: Sun, 10 Dec 2017 13:58:23 -0800 Cc: Linus Torvalds , Zhang Rui , Andrew Lutomirski , Thomas Gleixner , Jarkko Nikula , "Rafael J. Wysocki" , Linux Kernel Mailing List , the arch/x86 maintainers Message-Id: <76028A95-1CE1-49AA-9929-9C15FFC520EB@amacapital.net> References: <2809506.pL8kVbvXcY@aspire.rjw.lan> <1578405.51lzoSX1jh@aspire.rjw.lan> <20171209103325.GA13867@amd> <20171209220110.GA11496@amd> <20171210162305.GA10159@amd> <20171210185638.GA10363@amd> <20171210213804.GA4660@amd> To: Pavel Machek Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id vBALwVCm025877 Content-Length: 2445 Lines: 75 > On Dec 10, 2017, at 1:38 PM, Pavel Machek wrote: > > > After 4.15-rc2, suspend stopped working on Thinkpad X60. 5b06bbc > (unintentionally?) reordered stuff with respect to > fix_processor_context() on 32-bit and 64-bit. We undo that change on > 32-bit. > Can you explain what was wrong with the reordering? Your patch certainly *looks* incorrect. I'm guessing that the real issue is that 32-bit needs %fs restored early for TLS. > While we are at it, fix a comment. > > Signed-off-by: Pavel Machek > Fixes: 5b06bbcfc2c621da3009da8decb7511500c293ed > > diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c > index 5191de1..af7b613 100644 > --- a/arch/x86/power/cpu.c > +++ b/arch/x86/power/cpu.c > @@ -216,8 +216,8 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) > write_cr0(ctxt->cr0); > > /* > - * now restore the descriptor tables to their proper values > - * ltr is done i fix_processor_context(). > + * Now restore the descriptor tables to their proper values > + * ltr is done in fix_processor_context(). > */ > #ifdef CONFIG_X86_32 > load_idt(&ctxt->idt); > @@ -235,13 +235,11 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) > wrmsrl(MSR_GS_BASE, ctxt->gs_base); > #endif > > - fix_processor_context(); > - > +#ifdef CONFIG_X86_32 > /* > - * Restore segment registers. This happens after restoring the GDT > - * and LDT, which happen in fix_processor_context(). > + * Restore segment registers. > */ > -#ifdef CONFIG_X86_32 > + > loadsegment(es, ctxt->es); > loadsegment(fs, ctxt->fs); > loadsegment(gs, ctxt->gs); > @@ -252,8 +250,17 @@ static void notrace __restore_processor_state(struct saved_context *ctxt) > */ > if (boot_cpu_has(X86_FEATURE_SEP)) > enable_sep_cpu(); > + > + fix_processor_context(); > #else > /* CONFIG_X86_64 */ > + /* > + * Restore segment registers. This happens after restoring the GDT > + * and LDT, which happen in fix_processor_context(). > + */ > + > + fix_processor_context(); > + > asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds)); > asm volatile ("movw %0, %%es" :: "r" (ctxt->es)); > asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs)); > > > -- > (english) http://www.livejournal.com/~pavelmachek > (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html