Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752599AbdLKJ51 (ORCPT ); Mon, 11 Dec 2017 04:57:27 -0500 Received: from mail-oi0-f67.google.com ([209.85.218.67]:44043 "EHLO mail-oi0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751967AbdLKJ5Z (ORCPT ); Mon, 11 Dec 2017 04:57:25 -0500 X-Google-Smtp-Source: ACJfBotio/nA6aZVMrJ/MIv+3toufQ/R0dDa0d8VRGcEij2DUfquu0xWh1Jexd4xeoz7jTdcF+nMkWaNSFcRdCkYKyU= MIME-Version: 1.0 In-Reply-To: <9954ae4c-f3e9-ab6c-5c6b-cc914f246ab0@infradead.org> References: <9954ae4c-f3e9-ab6c-5c6b-cc914f246ab0@infradead.org> From: Masami Hiramatsu Date: Mon, 11 Dec 2017 18:57:04 +0900 Message-ID: Subject: Re: [PATCH] x86: update/correct opcode-map To: Randy Dunlap Cc: LKML , X86 ML , Masami Hiramatsu , Josh Poimboeuf Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2112 Lines: 82 Hi Randy, 2017-12-11 9:33 GMT+09:00 Randy Dunlap : > From: Randy Dunlap > > Update x86-opcode-map.txt based on the October 2017 Intel SDM publication. > Correct INVPID to INVVPID. > Add UD0, UD1, and UD2 instruction opcodes. Thanks for update! I have some comments on it. > > Signed-off-by: Randy Dunlap > Cc: Masami Hiramatsu > Cc: Josh Poimboeuf > Cc: x86 maintainers > --- > > arch/x86/lib/x86-opcode-map.txt | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > Are these following file updated automatically or manually? > ./tools/objtool/arch/x86/lib/x86-opcode-map.txt > ./tools/perf/util/intel-pt-decoder/x86-opcode-map.txt > > --- lnx-415-rc2.orig/arch/x86/lib/x86-opcode-map.txt > +++ lnx-415-rc2/arch/x86/lib/x86-opcode-map.txt > @@ -533,7 +533,7 @@ b5: LGS Gv,Mp > b6: MOVZX Gv,Eb > b7: MOVZX Gv,Ew > b8: JMPE (!F3) | POPCNT Gv,Ev (F3) > -b9: Grp10 (1A) > +b9: Grp10 (1A) [all UD1] Could you make this [all UD1] to just a comment? like "# all UD1". I would like to keep "[]" for other usecase. > ba: Grp8 Ev,Ib (1A) > bb: BTC Ev,Gv > bc: BSF Gv,Ev (!F3) | TZCNT Gv,Ev (F3) > @@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),( > fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1) > fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1) > fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1) > -ff: > +ff: UD0 > EndTable > > Table: 3-byte opcode 1 (0x0f 0x38) > @@ -717,7 +717,7 @@ AVXcode: 2 > 7e: vpermt2d/q Vx,Hx,Wx (66),(ev) > 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev) > 80: INVEPT Gy,Mdq (66) > -81: INVPID Gy,Mdq (66) > +81: INVVPID Gy,Mdq (66) > 82: INVPCID Gy,Mdq (66) > 83: vpmultishiftqb Vx,Hx,Wx (66),(ev) > 88: vexpandps/d Vpd,Wpd (66),(ev) > @@ -970,6 +970,7 @@ GrpTable: Grp9 > EndTable > > GrpTable: Grp10 > +# all are UD1 And could you expand this UD1 to a table? like 0: UD1 1: UD1 ... Thank you, > EndTable > > # Grp11A and Grp11B are expressed as Grp11 in Intel SDM > > -- Masami Hiramatsu mailto:masami.hiramatsu@gmail.com