Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752872AbdLKQ4N (ORCPT ); Mon, 11 Dec 2017 11:56:13 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:34251 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752586AbdLKQ4H (ORCPT ); Mon, 11 Dec 2017 11:56:07 -0500 X-Google-Smtp-Source: ACJfBov91P5Nm1O3smplKZI9FZYzCLhOa+HmAxRca0uDQhUR4xp/yAkhwWVHcF9tY9cC1H+1ORbVoA== From: Romain Izard To: Boris Brezillon , Michael Turquette , Stephen Boyd , Alexandre Belloni , Nicolas Ferre , Ludovic Desroches Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Romain Izard Subject: [PATCH v6 2/3] clk: at91: pmc: Save SCSR during suspend Date: Mon, 11 Dec 2017 17:55:34 +0100 Message-Id: <20171211165535.5126-3-romain.izard.pro@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171211165535.5126-1-romain.izard.pro@gmail.com> References: <20171211165535.5126-1-romain.izard.pro@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1555 Lines: 40 The contents of the System Clock Status Register (SCSR) needs to be restored into the System Clock Enable Register (SCER). As the bootloader will restore some clocks by itself, the issue can be missed as only the USB controller, the LCD controller, the Image Sensor controller and the programmable clocks will be impacted. Fix the obvious typo in the suspend/resume code, as the IMR register does not need to be saved twice. Signed-off-by: Romain Izard Acked-by: Nicolas Ferre --- drivers/clk/at91/pmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index 5c2b26de303e..07dc2861ad3f 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -86,7 +86,7 @@ static int pmc_suspend(void) { int i; - regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.scsr); + regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr); regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0); regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr); regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor); @@ -129,7 +129,7 @@ static void pmc_resume(void) if (pmc_cache.pllar != tmp) pr_warn("PLLAR was not configured properly by the firmware\n"); - regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.scsr); + regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr); regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0); regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr); regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor); -- 2.14.1