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Subject: Re: [RFC] irqchip: add support for LS1021A external interrupt lines
To: Rasmus Villemoes <rasmus.villemoes@prevas.dk>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>, Rob Herring <robh+dt@kernel.org>,
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From: Marc Zyngier <marc.zyngier@arm.com>
Organization: ARM Ltd
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Date: Mon, 11 Dec 2017 18:29:59 +0000
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On 11/12/17 09:30, Rasmus Villemoes wrote:
> On 2017-12-08 17:02, Marc Zyngier wrote:

[...]

>> Overall, it is a bit annoying that you just copied the driver altogether
>> instead of trying to allow the common stuff to be shared between
>> drivers. Most of this is just boilerplate code...
> 
> Yes, it did annoy me as well. However, the real meat of this is which
> bits of which register to poke to support a negative polarity irq, and
> there doesn't seem to be a good way to express that in DT. The register
> offset and the mapping from external irq# to the GIC one is reasonably
> easy (and would thus get rid of my NIRQ and INTPCR macros), but
> describing the mapping from IRQ# to the bit that needs to be set (or
> cleared) seems much harder. I cannot generalize from one example, so
> lacking documentation for any other Layerscape SOC, whatever I might
> come up with might not actually be useful for other hardware, making it
> rather pointless. But if you have any suggestions for how the DT
> bindings might look, I'm all ears.

You could have a list of <bit irq> pairs defining the mapping, for
example. But I'd encourage you to get in touch with the Freescale/NXP
folks and find out how this HW works. get_maintainers.pl gives me this:

Shawn Guo <shawnguo@kernel.org>
Tang Yuantian <Yuantian.Tang@nxp.com>
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Madalin Bucur <madalin.bucur@nxp.com>
Minghuan Lian <Minghuan.Lian@nxp.com>
Yuantian Tang <andy.tang@nxp.com>
Yangbo Lu <yangbo.lu@nxp.com>
"Horia Geantă" <horia.geanta@nxp.com>

I suggest you spam them and find out.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...