Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752642AbdLKSaH (ORCPT ); Mon, 11 Dec 2017 13:30:07 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:34106 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751585AbdLKSaC (ORCPT ); Mon, 11 Dec 2017 13:30:02 -0500 Subject: Re: [RFC] irqchip: add support for LS1021A external interrupt lines To: Rasmus Villemoes , Thomas Gleixner , Jason Cooper , Rob Herring , Mark Rutland Cc: Alexander Stein , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <48d2d08c-c57a-ce49-5958-0fd5ad4a2dc7@arm.com> <1512743580-15358-1-git-send-email-rasmus.villemoes@prevas.dk> <563e0aaa-faf9-ae6a-ccd4-2aa89d7e457b@prevas.dk> From: Marc Zyngier Organization: ARM Ltd Message-ID: <3b22d1ed-fe8f-b733-1543-86e89b493114@arm.com> Date: Mon, 11 Dec 2017 18:29:59 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <563e0aaa-faf9-ae6a-ccd4-2aa89d7e457b@prevas.dk> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1638 Lines: 41 On 11/12/17 09:30, Rasmus Villemoes wrote: > On 2017-12-08 17:02, Marc Zyngier wrote: [...] >> Overall, it is a bit annoying that you just copied the driver altogether >> instead of trying to allow the common stuff to be shared between >> drivers. Most of this is just boilerplate code... > > Yes, it did annoy me as well. However, the real meat of this is which > bits of which register to poke to support a negative polarity irq, and > there doesn't seem to be a good way to express that in DT. The register > offset and the mapping from external irq# to the GIC one is reasonably > easy (and would thus get rid of my NIRQ and INTPCR macros), but > describing the mapping from IRQ# to the bit that needs to be set (or > cleared) seems much harder. I cannot generalize from one example, so > lacking documentation for any other Layerscape SOC, whatever I might > come up with might not actually be useful for other hardware, making it > rather pointless. But if you have any suggestions for how the DT > bindings might look, I'm all ears. You could have a list of pairs defining the mapping, for example. But I'd encourage you to get in touch with the Freescale/NXP folks and find out how this HW works. get_maintainers.pl gives me this: Shawn Guo Tang Yuantian Hou Zhiqiang Madalin Bucur Minghuan Lian Yuantian Tang Yangbo Lu "Horia Geantă" I suggest you spam them and find out. Thanks, M. -- Jazz is not dead. It just smells funny...