Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752259AbdLLGYg (ORCPT ); Tue, 12 Dec 2017 01:24:36 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:27135 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1750955AbdLLGY2 (ORCPT ); Tue, 12 Dec 2017 01:24:28 -0500 X-UUID: 9bed6b9553e244568c40e3058e67be19-20171212 From: To: , , , , , CC: , , , Sean Wang Subject: [PATCH v2 0/4] add support of pinctrl to MT7622 SoC Date: Tue, 12 Dec 2017 14:24:17 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2438 Lines: 56 From: Sean Wang Changes since v1: - add changes for the suggestion in v1. - fix up the names for pin 14, 15, 71, 72, 93 and 94. - add function "watchdog". - change pin groups used by ethernet, i2s, led, pcie, spic, tdm and watchdog for refining the naming and reflecting the actual usage on the board. The patchset adds support for pinctrl on MT7622 SoC. patch 1: describe the hardware, also including the defintion for pins, groups and function. patch 2: add cleanup for keep drivers inside the independent menu. patch 3/4: add support for mt7622 SoC. The IO core found on the SoC has the registers for pinctrl, pinconf and gpio mixed up in the same register range. However, the IO core for the MT7622 SoC is completely distinct from anyone of previous MediaTek SoCs which already had support, such as the hardware internal, register address map and register detailed definition for each pin. Therefore, instead, the driver is being newly implemented by reusing generic methods provided from the core layer with GENERIC_PINCONF, GENERIC_PINCTRL_GROUPS, and GENERIC_PINMUX_FUNCTIONS for the sake of code simplicity and avoiding superfluous code. Where the function of pins determined by groups is utilized in this driver which can help developers less confused with what combinations of pins effective on the SoC and even reducing the mistakes during the integration of those relevant boards. As the gpio_chip handling is also only a few lines, the driver also implements the gpio functionality directly through GPIOLIB. Sean Wang (4): dt-bindings: pinctrl: add bindings for MediaTek MT7622 SoC pinctrl: mediatek: cleanup for placing all drivers under the menu pinctrl: mediatek: add pinctrl driver for MT7622 SoC pinctrl: mediatek: update MAINTAINERS entry with MediaTek pinctrl driver .../devicetree/bindings/pinctrl/pinctrl-mt7622.txt | 351 +++++ MAINTAINERS | 10 + drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/mediatek/Kconfig | 15 +- drivers/pinctrl/mediatek/Makefile | 3 +- drivers/pinctrl/mediatek/pinctrl-mt7622.c | 1595 ++++++++++++++++++++ 6 files changed, 1972 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7622.c -- 2.7.4