Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751641AbdLLIwB (ORCPT ); Tue, 12 Dec 2017 03:52:01 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:57088 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750731AbdLLIv6 (ORCPT ); Tue, 12 Dec 2017 03:51:58 -0500 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BCCD660218 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=mgautam@codeaurora.org Subject: Re: [PATCH v3 07/16] phy: qcom-qusb2: Add support for different register layouts To: Vivek Gautam , Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Yoshihiro Shimoda , Stephen Boyd , "open list:GENERIC PHY FRAMEWORK" References: <1511256206-1587-1-git-send-email-mgautam@codeaurora.org> <1511256206-1587-8-git-send-email-mgautam@codeaurora.org> <3c0dca03-bf9e-8747-8c31-546172f88d6f@codeaurora.org> From: Manu Gautam Message-ID: <3210de61-5094-ce04-5293-b701dc35dd49@codeaurora.org> Date: Tue, 12 Dec 2017 14:21:52 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <3c0dca03-bf9e-8747-8c31-546172f88d6f@codeaurora.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1511 Lines: 46 Hi Vivek, On 12/5/2017 3:53 PM, Vivek Gautam wrote: > > > On 11/21/2017 02:53 PM, Manu Gautam wrote: >> New version of QUSB2 PHY has some registers offset changed. >> Add support to have register layout for a target and update >> the same in phy_configuration. >> >> Signed-off-by: Manu Gautam >> --- >> ? drivers/phy/qualcomm/phy-qcom-qusb2.c | 131 ++++++++++++++++++++++++---------- >> ? 1 file changed, 95 insertions(+), 36 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c >> index 4a5b2a1..c0c5358 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c > [snip] >> ? /* >> @@ -198,7 +249,8 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) > > We need to add following change to qusb2_phy_set_tune2_param() > since we have register layout now. > > @@ -333,7 +334,7 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) > ??????? } > > ??????? /* Fused TUNE2 value is the higher nibble only */ > -?????? qusb2_setbits(qphy->base, QUSB2PHY_PORT_TUNE2, val[0] << 0x4); > +?????? qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], val[0] << 0x4); Thanks for catching this. Actually on qusb-v2 PHY, fused value is used to update TUNE1 instead of TUNE2 register. I will make changes accordingly. > ?} > > regards > Vivek > -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project