Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752509AbdLLUst (ORCPT ); Tue, 12 Dec 2017 15:48:49 -0500 Received: from mga11.intel.com ([192.55.52.93]:41205 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752263AbdLLUsq (ORCPT ); Tue, 12 Dec 2017 15:48:46 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,395,1508828400"; d="scan'208";a="158162847" Message-ID: <1513112704.11361.1.camel@megha-Z97X-UD7-TH> Subject: Re: [PATCH V2 3/3] x86, bm: Add documentation on Intel Branch Monitoring From: Megha Dey To: Jiri Olsa Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, andriy.shevchenko@linux.intel.com, kstewart@linuxfoundation.org, yu-cheng.yu@intel.com, len.brown@intel.com, gregkh@linuxfoundation.org, peterz@infradead.org, acme@kernel.org, alexander.shishkin@linux.intel.com, namhyung@kernel.org, vikas.shivappa@linux.intel.com, pombredanne@nexb.com, me@kylehuey.com, bp@suse.de, grzegorz.andrejczuk@intel.com, tony.luck@intel.com, corbet@lwn.net, ravi.v.shankar@intel.com Date: Tue, 12 Dec 2017 13:05:04 -0800 In-Reply-To: <20171120140746.GA23281@krava> References: <1510970046-25387-1-git-send-email-megha.dey@linux.intel.com> <1510970046-25387-4-git-send-email-megha.dey@linux.intel.com> <20171120140746.GA23281@krava> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3404 Lines: 73 On Mon, 2017-11-20 at 15:07 +0100, Jiri Olsa wrote: > On Fri, Nov 17, 2017 at 05:54:06PM -0800, Megha Dey wrote: > > SNIP > > > +IV. User-configurable inputs > > +============================ > > + > > +Several sysfs entries are provided in /sys/devices/intel_bm/ to configure > > +controls for the supported hardware heuristics. > > + > > +1. LBR freeze: /sys/devices/intel-bm/lbr_freeze > > + possible values are 0 or 1. By default this is disabled(0). When enabled, > > + an LBR freeze is observed on threshold trip > > + > > +2. Guest Disable: /sys/devices/intel-bm/guest_disable > > + Possible values are 0 or 1. By default it is 0. When set to ‘1’, branch > > + monitoring feature is disabled when operating at VMX non-root operation. > > + > > +3. Window size: /sys/devices/intel-bm/window_size > > + By default, window size is 1023. It can take values from 0 to 1023. This > > + represents the number of instructions to be executed before the event > > + counters are reset. > > + > > +4. Window count select: /sys/devices/intel-bm/window_cnt_sel > > + Possible values are: > > + ‘00 = instructions retired > > + ‘01 = branches retired > > + ‘10 = returned instructions retired > > + ‘11 = indirect branch instructions retired > > + By default, it has a value of 0. > > + > > +5. Count and mode: /sys/devices/intel-bm/cnt_and_mode > > + Possible values are 0 or 1. By default it is 0. When set to ‘1’, the > > + overall event triggering condition is true only if both enabled > > + counter’s threshold conditions are true. When ‘0’, the threshold > > + tripping condition is true if either enabled counter’s threshold is > > + true. If a counter is not enabled, then it does not factor into the > > + AND’ing logic > > + > > +6. Threshold: /sys/devices/intel-bm/threshold > > + An unsigned value of 0 to 127 is supported. The value 0 of counter > > + threshold will result in branch monitoring event signaled after every > > + instruction. By default, it has a value of 127. > > + > > +7. Mispredict counting behaviour: /sys/devices/intel-bm/mispred_evt_cnt > > + Possible values are: > > + 0 = mispredict events are counted in a window > > + 1 = mispredict events are counted based on a consecutive occurrence. > > + By default, it has a value of 0. > > you use all those value to configure the event: > > event->hw.bm_ctrl = (bm_window_size << BM_WINDOW_SIZE_SHIFT) | > (bm_guest_disable << BM_GUEST_DISABLE_SHIFT) | > (bm_lbr_freeze << BM_LBR_FREEZE_SHIFT) | > (bm_window_cnt_sel << BM_WINDOW_CNT_SEL_SHIFT) | > (bm_cnt_and_mode << BM_CNT_AND_MODE_SHIFT) | > BM_ENABLE; > event->hw.bm_counter_conf = (bm_threshold << BM_THRESHOLD_SHIFT) | > (bm_mispred_evt_cnt << BM_MISPRED_EVT_CNT_SHIFT) | > (cfg << BM_EVENT_TYPE_SHIFT) | BM_CNTR_ENABLE; > > I wonder you should place this under perf_event_attr::config/config1 > and define them in /sys/devices/intel_bm/format/... like we do for > cpu pmu > > then you could use perf stat -e like: '-e intel_bm/call-ret,threshold=...,lbr_freeze/' Thanks for the suggestion! I will implement this in the next patch set. > > jirka