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Date: Wed, 13 Dec 2017 16:19:50 +0800
From: Guo Ren <ren_guo@c-sky.com>
To: Greentime Hu <green.hu@gmail.com>
Cc: Greentime <greentime@andestech.com>,
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Subject: Re: [PATCH v3 09/33] nds32: Cache and TLB routines
Message-ID: <20171213081949.GA18840@gary-OptiPlex-3050>
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On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote:
 
> I think it should be fine if an interruption between mtsr_dsb and
> tlbop_rwr because this is a optimization by sw.

Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will
break that vaddr's pfn in the CPU tlb-buffer entry. When linux access the 
vaddr, it will get wrong data unless the entry has been replaced out.