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From: Greentime Hu <green.hu@gmail.com>
Date: Wed, 13 Dec 2017 16:30:41 +0800
Message-ID: <CAEbi=3eKH5JESwtadq4LKF3ZvmBi1QwUWpCTb0btierBST_cRQ@mail.gmail.com>
Subject: Re: [PATCH v3 09/33] nds32: Cache and TLB routines
To: Guo Ren <ren_guo@c-sky.com>
Cc: Greentime <greentime@andestech.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Arnd Bergmann <arnd@arndb.de>, linux-arch <linux-arch@vger.kernel.org>,
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        Linus Walleij <linus.walleij@linaro.org>,
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2017-12-13 16:19 GMT+08:00 Guo Ren <ren_guo@c-sky.com>:
> On Wed, Dec 13, 2017 at 01:45:02PM +0800, Greentime Hu wrote:
>
>> I think it should be fine if an interruption between mtsr_dsb and
>> tlbop_rwr because this is a optimization by sw.
>
> Fine? When there is an unexpected vaddr in SR_TLB_VPN, tlbop_rwr(*pte) will
> break that vaddr's pfn in the CPU tlb-buffer entry. When linux access the
> vaddr, it will get wrong data unless the entry has been replaced out.

Hi, Guo Ren:

Thanks. I get your point.
It is needed to be protected.
I will fix it in the next version patch.

if (vma->vm_mm == current->active_mm) {
        local_irq_save(flags);
        __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
        __nds32__tlbop_rwr(*pte);
        __nds32__isb();
        local_irq_restore(flags);
}